[coreboot-gerrit] Change in coreboot[master]: riscv: src/arch/riscv/bootblock.S

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27430


Change subject: riscv: src/arch/riscv/bootblock.S
......................................................................

riscv: src/arch/riscv/bootblock.S

Add an interface to support cache as ram.
Initialize stack pointer for each hart.

Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/bootblock.S
1 file changed, 24 insertions(+), 17 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27430/1

diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 0b5a2b2..0c30f6f 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -34,31 +34,38 @@
 	#
 	csrw mscratch, a1
 
-	# N.B. This only works on low 4G of the address space
+	# initialize cache as ram
+	call cache_as_ram
+
+	# initialize stack point for each hart
 	# and the stack must be page-aligned.
-	la sp, _estack
+	# 0xDEADBEEF used to check stack overflow
+	csrr a0, mhartid
+	la   t0, _stack
+	slli t1, a0, RISCV_PGSHIFT
+	add  t0, t0, t1
+	li   t1, 0xDEADBEEF
+	sd   t1, 0(t0)
+	li   t1, RISCV_PGSIZE - HLS_SIZE
+	add  sp, t0, t1
 
-	# poison the stack
-	la t1, _stack
-	li t0, 0xdeadbeef
-	sd t0, 0(t1)
-
-	# make room for HLS and initialize it
-	addi sp, sp, -HLS_SIZE
-
-	// Once again, the docs and toolchain disagree.
-	// Rather than get fancy I'll just lock this down
-	// until it all stabilizes.
-	//csrr a0, mhartid
-	csrr a0, 0xf14
-	call hls_init
-
+	# initialize entry of interrupt/exception
 	la t0, trap_entry
 	csrw mtvec, t0
 
+	# initialize hart-local storage
+	csrr a0, mhartid
+	call hls_init
+
 	# clear any pending interrupts
 	csrwi mip, 0
 
 	# set up the mstatus register for VM
 	call mstatus_init
 	tail main
+
+	// These codes need to be implemented on a specific SoC.
+	.weak cache_as_ram
+cache_as_ram:
+	ret
+

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409
Gerrit-Change-Number: 27430
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
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