[coreboot-gerrit] Change in coreboot[master]: google/cave: Add as a variant of glados
Matt DeVillier (Code Review)
gerrit at coreboot.org
Mon Jul 9 17:52:51 CEST 2018
Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27420
Change subject: google/cave: Add as a variant of glados
......................................................................
google/cave: Add as a variant of glados
Add google/cave (Asus Chromebook Flip C302SA) as a variant of
glados Skylake reference board:
- add cave-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]
Test: build/boot google/cave, verify correct functionality
Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/glados/Kconfig.name
A src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex
A src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex
A src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex
A src/mainboard/google/glados/variants/cave/Makefile.inc
A src/mainboard/google/glados/variants/cave/data.vbt
A src/mainboard/google/glados/variants/cave/devicetree.cb
A src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl
A src/mainboard/google/glados/variants/cave/include/variant/acpi/mainboard.asl
A src/mainboard/google/glados/variants/cave/include/variant/ec.h
A src/mainboard/google/glados/variants/cave/include/variant/gpio.h
A src/mainboard/google/glados/variants/cave/variant.c
13 files changed, 892 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/27420/1
diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 214ad13..412aefe 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -37,6 +37,7 @@
config MAINBOARD_PART_NUMBER
string
default "Caroline" if BOARD_GOOGLE_CAROLINE
+ default "Cave" if BOARD_GOOGLE_CAVE
default "Chell" if BOARD_GOOGLE_CHELL
default "Glados" if BOARD_GOOGLE_GLADOS
default "Lars" if BOARD_GOOGLE_LARS
@@ -49,6 +50,7 @@
config VARIANT_DIR
string
default "caroline" if BOARD_GOOGLE_CAROLINE
+ default "cave" if BOARD_GOOGLE_CAVE
default "chell" if BOARD_GOOGLE_CHELL
default "glados" if BOARD_GOOGLE_GLADOS
default "lars" if BOARD_GOOGLE_LARS
@@ -57,6 +59,7 @@
config DEVICETREE
string
default "variants/caroline/devicetree.cb" if BOARD_GOOGLE_CAROLINE
+ default "variants/cave/devicetree.cb" if BOARD_GOOGLE_CAVE
default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL
default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS
default "variants/lars/devicetree.cb" if BOARD_GOOGLE_LARS
@@ -91,6 +94,7 @@
string
depends on CHROMEOS
default "CAROLINE TEST 0958" if BOARD_GOOGLE_CAROLINE
+ default "CAVE TEST 9629" if BOARD_GOOGLE_CAVE
default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL
default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
default "LARS TEST 5001" if BOARD_GOOGLE_LARS
diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name
index 8538a2b..d20230e 100644
--- a/src/mainboard/google/glados/Kconfig.name
+++ b/src/mainboard/google/glados/Kconfig.name
@@ -9,6 +9,12 @@
select SAR_ENABLE
select USE_SAR
+config BOARD_GOOGLE_CAVE
+ bool "-> Cave (Asus Chromebook Flip C302SA)"
+ select BOARD_GOOGLE_BASEBOARD_GLADOS
+ select DRIVERS_GENERIC_MAX98357A
+ select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS
+
config BOARD_GOOGLE_CHELL
bool "-> Chell (HP Chromebook 13 G1)"
select BOARD_GOOGLE_BASEBOARD_GLADOS
diff --git a/src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex b/src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex
new file mode 100644
index 0000000..a4dbc16
--- /dev/null
+++ b/src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex
@@ -0,0 +1,32 @@
+91 20 F1 03 05 1A 05 0A
+03 11 01 08 09 00 00 05
+78 78 90 50 90 11 50 E0
+90 06 3C 3C 01 90 00 00
+00 31 CA FA 00 00 00 A8
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00
+00 00 00 00 00 00 2C 2A
+4D 54 35 32 4C 31 47 33
+32 44 34 50 47 2D 31 30
+37 20 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex b/src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex
new file mode 100644
index 0000000..79970c9
--- /dev/null
+++ b/src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex
@@ -0,0 +1,32 @@
+91 20 F1 03 05 19 05 03
+03 11 01 08 09 00 00 05
+78 78 90 50 90 11 50 E0
+90 06 3C 3C 01 90 00 00
+00 10 CA FA 00 00 00 A8
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 75 8C
+4D 54 35 32 4C 32 35 36
+4D 33 32 44 31 50 46 2D
+31 30 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex b/src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex
new file mode 100644
index 0000000..2753709
--- /dev/null
+++ b/src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex
@@ -0,0 +1,32 @@
+91 20 F1 03 05 19 05 0B
+03 11 01 08 09 00 00 05
+78 78 90 50 90 11 50 E0
+90 06 3C 3C 01 90 00 00
+00 21 CA FA 00 00 00 A8
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 3D 51
+4D 54 35 32 4C 35 31 32
+4D 33 32 44 32 50 46 2D
+31 30 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glados/variants/cave/Makefile.inc b/src/mainboard/google/glados/variants/cave/Makefile.inc
new file mode 100644
index 0000000..f3b52c2
--- /dev/null
+++ b/src/mainboard/google/glados/variants/cave/Makefile.inc
@@ -0,0 +1,43 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Google Inc.
+## Copyright (C) 2016 Intel Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += variant.c
+ramstage-y += variant.c
+smm-y += variant.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# SPD data by index. No method for board identification yet
+SPD_SOURCES = micron_4GiB_dimm_MT52L256M32D1PF # 0b0000
+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001
+SPD_SOURCES += micron_8GiB_dimm_MT52L512M32D2PF # 0b0010
+SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011
+SPD_SOURCES += micron_16GiB_dimm_MT52L1G32D4PG # 0b0100
+SPD_SOURCES += hynix_dimm_H9CCNNNCLTMLAR # 0b0101
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/glados/variants/cave/data.vbt b/src/mainboard/google/glados/variants/cave/data.vbt
new file mode 100644
index 0000000..02e1cd1
--- /dev/null
+++ b/src/mainboard/google/glados/variants/cave/data.vbt
Binary files differ
diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb
new file mode 100644
index 0000000..f6ba051
--- /dev/null
+++ b/src/mainboard/google/glados/variants/cave/devicetree.cb
@@ -0,0 +1,304 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "0"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "2"
+ register "IshEnable" = "0"
+ register "PttSwitch" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "1" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "1"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 5 Domains
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
+ #| IccMax | 4A | 24A | 24A | 24A | 24A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(4),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_RING]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ }"
+
+ # Enable Root port 1
+ register "PcieRpEnable[0]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[0]" = "1"
+ # RP 1 uses SRCCLKREQ1#
+ register "PcieRpClkReqNumber[0]" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port (board)
+ register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (flex)
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Type-A Port 1
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A Port 2
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (board)
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (flex)
+ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A Port 1
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoPci,
+ }"
+
+ # I2C4 is 1.8V
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
+
+ # PL2 override 15W
+ register "tdp_pl2_override" = "15"
+
+ register "tcc_offset" = "10" # TCC of 90C
+
+ # Send an extra VR mailbox command for the supported MPS IMVP8 model
+ register "SendVrMbxCmd" = "1"
+
+ # Use default SD card detect GPIO configuration
+ register "sdcard_cd_gpio_default" = "GPP_A7"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ device i2c 10 on end
+ end
+ end # I2C #0
+ device pci 15.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
+ register "wake" = "GPE0_DW0_05"
+ device i2c 15 on end
+ end
+ end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on
+ chip drivers/i2c/nau8825
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"
+ register "jkdet_enable" = "1"
+ register "jkdet_pull_enable" = "0" # R389
+ register "jkdet_polarity" = "1" # ActiveLow
+ register "vref_impedance" = "2" # 125kOhm
+ register "micbias_voltage" = "6" # 2.754
+ register "sar_threshold_num" = "4"
+ register "sar_threshold[0]" = "0x0c"
+ register "sar_threshold[1]" = "0x1e"
+ register "sar_threshold[2]" = "0x38"
+ register "sar_threshold[3]" = "0x60"
+ register "sar_hysteresis" = "1"
+ register "sar_voltage" = "0" # VDDA
+ register "sar_compare_time" = "0" # 500ns
+ register "sar_sampling_time" = "0" # 2us
+ register "short_key_debounce" = "2" # 100ms
+ register "jack_insert_debounce" = "7" # 512ms
+ register "jack_eject_debounce" = "7" # 512ms
+ device i2c 1a on end
+ end
+ end # I2C #4
+ device pci 1c.0 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW0_16"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 on end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 on end # SDCard
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..33b25a4
--- /dev/null
+++ b/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 99
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "WiFi"
+#define DPTF_TSR0_PASSIVE 50
+#define DPTF_TSR0_CRITICAL 80
+#define DPTF_TSR0_TABLET_PASSIVE 52
+#define DPTF_TSR0_TABLET_CRITICAL 80
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "PD"
+#define DPTF_TSR1_PASSIVE 50
+#define DPTF_TSR1_CRITICAL 80
+#define DPTF_TSR1_TABLET_PASSIVE 52
+#define DPTF_TSR1_TABLET_CRITICAL 80
+
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "DRAM"
+#define DPTF_TSR2_PASSIVE 50
+#define DPTF_TSR2_CRITICAL 80
+#define DPTF_TSR2_TABLET_PASSIVE 52
+#define DPTF_TSR2_TABLET_CRITICAL 80
+
+#define DPTF_TSR3_SENSOR_ID 4
+#define DPTF_TSR3_SENSOR_NAME "Charger"
+#define DPTF_TSR3_PASSIVE 68
+#define DPTF_TSR3_CRITICAL 85
+#define DPTF_TSR3_TABLET_PASSIVE 68
+#define DPTF_TSR3_TABLET_CRITICAL 85
+
+/* Enable DPTF charger control */
+#define DPTF_ENABLE_CHARGER
+
+/* SKL-Y is Fanless design. */
+#undef DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x1338, "mA", 0 }, /* 4920mA (MAX) */
+ Package () { 0, 0, 0, 0, 39, 0x9C0, "mA", 0 }, /* 2496mA */
+ Package () { 0, 0, 0, 0, 28, 0x700, "mA", 0 }, /* 1792mA */
+ Package () { 0, 0, 0, 0, 19, 0x4C0, "mA", 0 }, /* 1216mA */
+ Package () { 0, 0, 0, 0, 13, 0x340, "mA", 0 }, /* 832mA */
+ Package () { 0, 0, 0, 0, 10, 0x280, "mA", 0 }, /* 640mA */
+ Package () { 0, 0, 0, 0, 6, 0x180, "mA", 0 }, /* 384mA */
+ Package () { 0, 0, 0, 0, 2, 0x80, "mA", 0 }, /* 124mA */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 100, 0, 0, 0, 0 },
+
+ /* Charger Effect on Temp Sensor 3 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 100, 50, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 10000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 8000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/src/mainboard/google/glados/variants/cave/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/cave/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/google/glados/variants/cave/include/variant/acpi/mainboard.asl
diff --git a/src/mainboard/google/glados/variants/cave/include/variant/ec.h b/src/mainboard/google/glados/variants/cave/include/variant/ec.h
new file mode 100644
index 0000000..dfb05a3
--- /dev/null
+++ b/src/mainboard/google/glados/variants/cave/include/variant/ec.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+/* EC ENABLE TABLET EVENT */
+#define EC_ENABLE_TABLET_EVENT
+
diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h
new file mode 100644
index 0000000..6674b0e
--- /dev/null
+++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h
@@ -0,0 +1,246 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* MAX98357A SD_MODE */
+#define GPIO_SPEAKER_MAXIM_AMP_SDMODE GPP_E3
+
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_C6
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP GPP_C23
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_C12
+#define GPIO_MEM_CONFIG_1 GPP_C13
+#define GPIO_MEM_CONFIG_2 GPP_C14
+#define GPIO_MEM_CONFIG_3 GPP_C15
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_WLAN_WAKE GPE0_DW0_16
+
+/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_TOUCHPAD_WAKE GPE0_DW0_05
+
+/* Input device interrupt configuration */
+#define TOUCHPAD_INT_L GPP_B3_IRQ
+#define TOUCHSCREEN_INT_L GPP_E7_IRQ
+#define MIC_INT_L GPP_F10_IRQ
+
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
+#define EC_SCI_GPI GPE0_DW2_16
+#define EC_SMI_GPI GPP_E15
+
+/* Power rail control signals. */
+#define EN_PP3300_KEPLER GPP_C11
+#define EN_PP3300_DX_TOUCH GPP_C22
+#define EN_PP3300_DX_EMMC GPP_D5
+#define EN_PP1800_DX_EMMC GPP_D6
+#define EN_PP3300_DX_CAM GPP_D12
+
+/* SD controller needs additional card detect GPIO to support RTD3 */
+#define GPIO_SD_CARD_DETECT GPP_A7
+
+#ifndef __ACPI__
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
+/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
+/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
+/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
+/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),
+/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
+/* PME# */ PAD_CFG_NC(GPP_A11),
+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
+/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
+/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
+/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
+/* VRALERT# */ PAD_CFG_NC(GPP_B2),
+/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD */
+/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
+/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */
+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */
+/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7),
+/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
+/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),
+/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
+/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* SPKR */ PAD_CFG_NC(GPP_B14),
+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
+/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */
+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
+/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
+/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
+/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
+/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22),
+/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP),
+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
+/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
+/* SMBALERT# */ PAD_CFG_NC(GPP_C2),
+/* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP),
+/* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP),
+/* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),
+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
+/* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP),
+/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
+/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
+/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
+/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
+/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
+/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
+/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
+/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */
+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TRACKPAD */
+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
+/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),
+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),
+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),
+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),
+/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
+/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */
+/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */
+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
+ PAD_CFG_NC(GPP_D9),
+ PAD_CFG_NC(GPP_D10),
+ PAD_CFG_NC(GPP_D11),
+ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
+/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
+/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+/* TS_SPI_IO2 */ PAD_CFG_NC(GPP_D21),
+/* TS_SPI_IO3 */ PAD_CFG_NC(GPP_D22),
+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */
+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
+/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
+/* CPU_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), /* AUDIO_DB_ID */
+/* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* TOUCH_RESET */
+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
+/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */
+/* SATALED# */ PAD_CFG_NC(GPP_E8),
+/* USB2_OCO# */ PAD_CFG_NC(GPP_E9),
+/* USB2_OC1# */ PAD_CFG_NC(GPP_E10),
+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */
+/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */
+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+ PAD_CFG_NC(GPP_E22),
+ PAD_CFG_NC(GPP_E23),
+/*
+ * The next 4 pads are for bit banging the amplifiers. They are connected
+ * together with i2s0 signals. For default behavior of i2s make these
+ * gpio inupts.
+ */
+/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
+/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
+/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
+/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */
+/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */
+/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
+/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),
+/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 1, DEEP),
+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
+/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+/* LAN_WAKE# */ PAD_CFG_NF(GPD2, 20K_PU, DEEP, NF1), /* EC_PCH_WAKE_L */
+/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+/* SLP_S3# */ PAD_CFG_NF(GPD4, 20K_PU, DEEP, NF1),
+/* SLP_S4# */ PAD_CFG_NF(GPD5, 20K_PU, DEEP, NF1),
+/* SLP_A# */ PAD_CFG_NF(GPD6, 20K_PU, DEEP, NF1),
+ PAD_CFG_NC(GPD7),
+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* SLP_WLAN# */ PAD_CFG_NC(GPD9),
+/* SLP_S5# */ PAD_CFG_NF(GPD10, 20K_PU, DEEP, NF1),
+/* LANPHYC */ PAD_CFG_NC(GPD11),
+};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c
new file mode 100644
index 0000000..2ce0a90
--- /dev/null
+++ b/src/mainboard/google/glados/variants/cave/variant.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variant.h>
+#include <gpio.h>
+#include <stdint.h>
+#include <string.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <variant/gpio.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
+
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 200, 81, 162 };
+
+ /* Rcomp target */
+ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
+
+ memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+ memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+ memcpy(pei_data->RcompResistor, RcompResistor,
+ sizeof(RcompResistor));
+ memcpy(pei_data->RcompTarget, RcompTarget,
+ sizeof(RcompTarget));
+}
+
+void mainboard_gpio_smi_sleep(void)
+{
+ int i;
+
+ /* Power down the rails on any sleep type. */
+ gpio_t active_high_signals[] = {
+ EN_PP3300_KEPLER,
+ EN_PP3300_DX_TOUCH,
+ EN_PP3300_DX_EMMC,
+ EN_PP1800_DX_EMMC,
+ EN_PP3300_DX_CAM,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
+ gpio_set(active_high_signals[i], 0);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a
Gerrit-Change-Number: 27420
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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