<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27420">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/cave: Add as a variant of glados<br><br>Add google/cave (Asus Chromebook Flip C302SA) as a variant of<br>glados Skylake reference board:<br>- add cave-specific DPTF, EC config, GPIO config, Kconfig,<br> NHLT config, PEI data, VBT, SPD data, and devicetree<br><br>Adapted from Chromium branch firmware-glados-7820.B, commit<br>b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]<br><br>Test: build/boot google/cave, verify correct functionality<br><br>Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/glados/Kconfig<br>M src/mainboard/google/glados/Kconfig.name<br>A src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex<br>A src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex<br>A src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex<br>A src/mainboard/google/glados/variants/cave/Makefile.inc<br>A src/mainboard/google/glados/variants/cave/data.vbt<br>A src/mainboard/google/glados/variants/cave/devicetree.cb<br>A src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl<br>A src/mainboard/google/glados/variants/cave/include/variant/acpi/mainboard.asl<br>A src/mainboard/google/glados/variants/cave/include/variant/ec.h<br>A src/mainboard/google/glados/variants/cave/include/variant/gpio.h<br>A src/mainboard/google/glados/variants/cave/variant.c<br>13 files changed, 892 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/27420/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig</span><br><span>index 214ad13..412aefe 100644</span><br><span>--- a/src/mainboard/google/glados/Kconfig</span><br><span>+++ b/src/mainboard/google/glados/Kconfig</span><br><span>@@ -37,6 +37,7 @@</span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span> default "Caroline" if BOARD_GOOGLE_CAROLINE</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Cave" if BOARD_GOOGLE_CAVE</span><br><span> default "Chell" if BOARD_GOOGLE_CHELL</span><br><span> default "Glados" if BOARD_GOOGLE_GLADOS</span><br><span> default "Lars" if BOARD_GOOGLE_LARS</span><br><span>@@ -49,6 +50,7 @@</span><br><span> config VARIANT_DIR</span><br><span> string</span><br><span> default "caroline" if BOARD_GOOGLE_CAROLINE</span><br><span style="color: hsl(120, 100%, 40%);">+ default "cave" if BOARD_GOOGLE_CAVE</span><br><span> default "chell" if BOARD_GOOGLE_CHELL</span><br><span> default "glados" if BOARD_GOOGLE_GLADOS</span><br><span> default "lars" if BOARD_GOOGLE_LARS</span><br><span>@@ -57,6 +59,7 @@</span><br><span> config DEVICETREE</span><br><span> string</span><br><span> default "variants/caroline/devicetree.cb" if BOARD_GOOGLE_CAROLINE</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/cave/devicetree.cb" if BOARD_GOOGLE_CAVE</span><br><span> default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL</span><br><span> default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS</span><br><span> default "variants/lars/devicetree.cb" if BOARD_GOOGLE_LARS</span><br><span>@@ -91,6 +94,7 @@</span><br><span> string</span><br><span> depends on CHROMEOS</span><br><span> default "CAROLINE TEST 0958" if BOARD_GOOGLE_CAROLINE</span><br><span style="color: hsl(120, 100%, 40%);">+ default "CAVE TEST 9629" if BOARD_GOOGLE_CAVE</span><br><span> default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL</span><br><span> default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS</span><br><span> default "LARS TEST 5001" if BOARD_GOOGLE_LARS</span><br><span>diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name</span><br><span>index 8538a2b..d20230e 100644</span><br><span>--- a/src/mainboard/google/glados/Kconfig.name</span><br><span>+++ b/src/mainboard/google/glados/Kconfig.name</span><br><span>@@ -9,6 +9,12 @@</span><br><span> select SAR_ENABLE</span><br><span> select USE_SAR</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_CAVE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> Cave (Asus Chromebook Flip C302SA)"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_GOOGLE_BASEBOARD_GLADOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_GENERIC_MAX98357A</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config BOARD_GOOGLE_CHELL</span><br><span> bool "-> Chell (HP Chromebook 13 G1)"</span><br><span> select BOARD_GOOGLE_BASEBOARD_GLADOS</span><br><span>diff --git a/src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex b/src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..a4dbc16</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+91 20 F1 03 05 1A 05 0A</span><br><span style="color: hsl(120, 100%, 40%);">+03 11 01 08 09 00 00 05</span><br><span style="color: hsl(120, 100%, 40%);">+78 78 90 50 90 11 50 E0</span><br><span style="color: hsl(120, 100%, 40%);">+90 06 3C 3C 01 90 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 31 CA FA 00 00 00 A8</span><br><span style="color: hsl(120, 100%, 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40%);">+00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex b/src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..79970c9</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+91 20 F1 03 05 19 05 03</span><br><span style="color: hsl(120, 100%, 40%);">+03 11 01 08 09 00 00 05</span><br><span style="color: hsl(120, 100%, 40%);">+78 78 90 50 90 11 50 E0</span><br><span style="color: hsl(120, 100%, 40%);">+90 06 3C 3C 01 90 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 10 CA FA 00 00 00 A8</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span 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a/src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex b/src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..2753709</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+91 20 F1 03 05 19 05 0B</span><br><span style="color: hsl(120, 100%, 40%);">+03 11 01 08 09 00 00 05</span><br><span style="color: hsl(120, 100%, 40%);">+78 78 90 50 90 11 50 E0</span><br><span style="color: hsl(120, 100%, 40%);">+90 06 3C 3C 01 90 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 21 CA FA 00 00 00 A8</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 80 2c 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 3D 51</span><br><span style="color: hsl(120, 100%, 40%);">+4D 54 35 32 4C 35 31 32</span><br><span style="color: hsl(120, 100%, 40%);">+4D 33 32 44 32 50 46 2D</span><br><span style="color: hsl(120, 100%, 40%);">+31 30 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/glados/variants/cave/Makefile.inc b/src/mainboard/google/glados/variants/cave/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..f3b52c2</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/cave/Makefile.inc</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2016 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2016 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += variant.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += variant.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += variant.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_BIN = $(obj)/spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# SPD data by index. No method for board identification yet</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES = micron_4GiB_dimm_MT52L256M32D1PF # 0b0000</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += micron_8GiB_dimm_MT52L512M32D2PF # 0b0010</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += micron_16GiB_dimm_MT52L1G32D4PG # 0b0100</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += hynix_dimm_H9CCNNNCLTMLAR # 0b0101</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Include spd ROM data</span><br><span style="color: hsl(120, 100%, 40%);">+$(SPD_BIN): $(SPD_DEPS)</span><br><span style="color: hsl(120, 100%, 40%);">+ for f in $+; \</span><br><span style="color: hsl(120, 100%, 40%);">+ do for c in $$(cat $$f | grep -v ^#); \</span><br><span style="color: hsl(120, 100%, 40%);">+ do printf $$(printf '\%o' 0x$$c); \</span><br><span style="color: hsl(120, 100%, 40%);">+ done; \</span><br><span style="color: hsl(120, 100%, 40%);">+ done > $@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cbfs-files-y += spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-file := $(SPD_BIN)</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-type := spd</span><br><span>diff --git a/src/mainboard/google/glados/variants/cave/data.vbt b/src/mainboard/google/glados/variants/cave/data.vbt</span><br><span>new file mode 100644</span><br><span>index 0000000..02e1cd1</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/cave/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..f6ba051</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/cave/devicetree.cb</span><br><span>@@ -0,0 +1,304 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/skylake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable deep Sx states</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_ac" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_dc" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_ac" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_dc" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "GPP_E"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0201"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable "Intel Speed Shift Technology"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ProbelessTrace" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableLan" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableSata" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataMode" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableAzalia" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IoBufferOwnership" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableTraceHub" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SsicPortEnable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Cio2Enable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsSdCardEnabled" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IshEnable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PttSwitch" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "InternalGfx" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SkipExtGfxScan" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Device4Enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIrqConfigSirqEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS3MinAssert" = "2" # 50ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS4MinAssert" = "1" # 1s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpSusMinAssert" = "1" # 500ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpAMinAssert" = "3" # 2s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmTimerDisabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # VR Settings Configuration for 5 Domains</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------------+-------------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------------+-------------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| IccMax | 4A | 24A | 24A | 24A | 24A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------------+-------------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(4),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(4),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_IA_CORE]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(24),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_RING]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(24),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_UNSLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(24),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_SLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(24),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 1 uses SRCCLKREQ1#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port (board)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (flex)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Type-A Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (board)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (flex)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Must leave UART0 enabled or SD/eMMC will not work as PCI</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoDevMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C1] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C4] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart2] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # I2C4 is 1.8V</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PL2 override 15W</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tdp_pl2_override" = "15"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tcc_offset" = "10" # TCC of 90C</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Send an extra VR mailbox command for the supported MPS IMVP8 model</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SendVrMbxCmd" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Use default SD card detect GPIO configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdcard_cd_gpio_default" = "GPP_A7"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Lock Down</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/generic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""ELAN0001""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""ELAN Touchscreen""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 10 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/generic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""ELAN0000""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""ELAN Touchpad""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW0_05"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 15 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 off end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/nau8825</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jkdet_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jkdet_pull_enable" = "0" # R389</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jkdet_polarity" = "1" # ActiveLow</span><br><span style="color: hsl(120, 100%, 40%);">+ register "vref_impedance" = "2" # 125kOhm</span><br><span style="color: hsl(120, 100%, 40%);">+ register "micbias_voltage" = "6" # 2.754</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold_num" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold[0]" = "0x0c"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold[1]" = "0x1e"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold[2]" = "0x38"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold[3]" = "0x60"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_hysteresis" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_voltage" = "0" # VDDA</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_compare_time" = "0" # 500ns</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_sampling_time" = "0" # 2us</span><br><span style="color: hsl(120, 100%, 40%);">+ register "short_key_debounce" = "2" # 100ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_insert_debounce" = "7" # 512ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_eject_debounce" = "7" # 512ms</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 1a on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW0_16"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCI Express Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCI Express Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCI Express Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCI Express Port 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCI Express Port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 off end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.4 on end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.5 off end # SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.6 on end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/google/chromeec</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/max98357a</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdmode_delay" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ device generic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..33b25a4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl</span><br><span>@@ -0,0 +1,102 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_PASSIVE 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_CRITICAL 99</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_ID 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_NAME "WiFi"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_PASSIVE 50</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_TABLET_PASSIVE 52</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_TABLET_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_ID 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_NAME "PD"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_PASSIVE 50</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_TABLET_PASSIVE 52</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_TABLET_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_SENSOR_ID 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_SENSOR_NAME "DRAM"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_PASSIVE 50</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_TABLET_PASSIVE 52</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_TABLET_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_SENSOR_ID 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_SENSOR_NAME "Charger"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_PASSIVE 68</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_CRITICAL 85</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_TABLET_PASSIVE 68</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_TABLET_CRITICAL 85</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable DPTF charger control */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SKL-Y is Fanless design. */</span><br><span style="color: hsl(120, 100%, 40%);">+#undef DPTF_ENABLE_FAN_CONTROL</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Charger performance states, board-specific values from charger and EC */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (CHPS, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 255, 0x1338, "mA", 0 }, /* 4920mA (MAX) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 39, 0x9C0, "mA", 0 }, /* 2496mA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 28, 0x700, "mA", 0 }, /* 1792mA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 19, 0x4C0, "mA", 0 }, /* 1216mA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 13, 0x340, "mA", 0 }, /* 832mA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 10, 0x280, "mA", 0 }, /* 640mA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 6, 0x180, "mA", 0 }, /* 384mA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 2, 0x80, "mA", 0 }, /* 124mA */</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (DTRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Effect on Temp Sensor 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Effect on Temp Sensor 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Effect on Temp Sensor 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 100, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Charger Effect on Temp Sensor 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 100, 50, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (MPPC, Package ()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x2, /* Revision */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1600, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 10000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 200 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 8000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 8000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span>diff --git a/src/mainboard/google/glados/variants/cave/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/cave/include/variant/acpi/mainboard.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/cave/include/variant/acpi/mainboard.asl</span><br><span>diff --git a/src/mainboard/google/glados/variants/cave/include/variant/ec.h b/src/mainboard/google/glados/variants/cave/include/variant/ec.h</span><br><span>new file mode 100644</span><br><span>index 0000000..dfb05a3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/cave/include/variant/ec.h</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable EC backed ALS device in ACPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_ALS_DEVICE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable EC backed Keyboard Backlight in ACPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_KEYBOARD_BACKLIGHT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC ENABLE TABLET EVENT */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_TABLET_EVENT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..6674b0e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h</span><br><span>@@ -0,0 +1,246 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* MAX98357A SD_MODE */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_SPEAKER_MAXIM_AMP_SDMODE GPP_E3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC in RW */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_EC_IN_RW GPP_C6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* BIOS Flash Write Protect */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PCH_WP GPP_C23</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory configuration board straps */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_0 GPP_C12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_1 GPP_C13</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_2 GPP_C14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_3 GPP_C15</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_EC_WAKE GPE0_LAN_WAK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_WLAN_WAKE GPE0_DW0_16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_TOUCHPAD_WAKE GPE0_DW0_05</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Input device interrupt configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOUCHPAD_INT_L GPP_B3_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOUCHSCREEN_INT_L GPP_E7_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIC_INT_L GPP_F10_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SCI_GPI GPE0_DW2_16</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SMI_GPI GPP_E15</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Power rail control signals. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EN_PP3300_KEPLER GPP_C11</span><br><span style="color: hsl(120, 100%, 40%);">+#define EN_PP3300_DX_TOUCH GPP_C22</span><br><span style="color: hsl(120, 100%, 40%);">+#define EN_PP3300_DX_EMMC GPP_D5</span><br><span style="color: hsl(120, 100%, 40%);">+#define EN_PP1800_DX_EMMC GPP_D6</span><br><span style="color: hsl(120, 100%, 40%);">+#define EN_PP3300_DX_CAM GPP_D12</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD controller needs additional card detect GPIO to support RTD3 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_SD_CARD_DETECT GPP_A7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PME# */ PAD_CFG_NC(GPP_A11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* VRALERT# */ PAD_CFG_NC(GPP_B2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPKR */ PAD_CFG_NC(GPP_B14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBALERT# */ PAD_CFG_NC(GPP_C2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RXD */ PAD_CFG_NC(GPP_C8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_TXD */ PAD_CFG_NC(GPP_C9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TRACKPAD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* FASHTRIG */ PAD_CFG_NC(GPP_D4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D9),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D10),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D11),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TS_SPI_IO2 */ PAD_CFG_NC(GPP_D21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TS_SPI_IO3 */ PAD_CFG_NC(GPP_D22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), /* AUDIO_DB_ID */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* TOUCH_RESET */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_NC(GPP_E8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OCO# */ PAD_CFG_NC(GPP_E9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC1# */ PAD_CFG_NC(GPP_E10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E22),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E23),</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The next 4 pads are for bit banging the amplifiers. They are connected</span><br><span style="color: hsl(120, 100%, 40%);">+ * together with i2s0 signals. For default behavior of i2s make these</span><br><span style="color: hsl(120, 100%, 40%);">+ * gpio inupts.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAN_WAKE# */ PAD_CFG_NF(GPD2, 20K_PU, DEEP, NF1), /* EC_PCH_WAKE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S3# */ PAD_CFG_NF(GPD4, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S4# */ PAD_CFG_NF(GPD5, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_A# */ PAD_CFG_NF(GPD6, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_WLAN# */ PAD_CFG_NC(GPD9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S5# */ PAD_CFG_NF(GPD10, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LANPHYC */ PAD_CFG_NC(GPD11),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in romstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c</span><br><span>new file mode 100644</span><br><span>index 0000000..2ce0a90</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/cave/variant.c</span><br><span>@@ -0,0 +1,67 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variant.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pei_data.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pei_wrapper.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_pei_data(struct pei_data *pei_data)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQ byte map */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dq_map[2][12] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQS CPU<>DRAM map */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map[2][8] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 1, 3, 2, 4, 5, 6, 7 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 4, 5, 2, 3, 6, 7 } };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rcomp resistor */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 RcompResistor[3] = { 200, 81, 162 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rcomp target */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(pei_data->RcompResistor, RcompResistor,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(RcompResistor));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(pei_data->RcompTarget, RcompTarget,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(RcompTarget));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_gpio_smi_sleep(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Power down the rails on any sleep type. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_t active_high_signals[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ EN_PP3300_KEPLER,</span><br><span style="color: hsl(120, 100%, 40%);">+ EN_PP3300_DX_TOUCH,</span><br><span style="color: hsl(120, 100%, 40%);">+ EN_PP3300_DX_EMMC,</span><br><span style="color: hsl(120, 100%, 40%);">+ EN_PP1800_DX_EMMC,</span><br><span style="color: hsl(120, 100%, 40%);">+ EN_PP3300_DX_CAM,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set(active_high_signals[i], 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27420">change 27420</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27420"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a </div>
<div style="display:none"> Gerrit-Change-Number: 27420 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>