[coreboot-gerrit] Change in coreboot[master]: mediatek: Share MMU operation code among similar SOCs
Tristan Hsieh (Code Review)
gerrit at coreboot.org
Wed Jul 4 09:10:05 CEST 2018
Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27349
Change subject: mediatek: Share MMU operation code among similar SOCs
......................................................................
mediatek: Share MMU operation code among similar SOCs
Refactor MMU operation code which will be reused among similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f
Signed-off-by: Tristan Shieh <tristan.shieh at mediatek.com>
---
M src/mainboard/google/oak/romstage.c
R src/soc/mediatek/common/include/soc/mmu_operations.h
A src/soc/mediatek/common/mmu_operations.c
M src/soc/mediatek/mt8173/Makefile.inc
M src/soc/mediatek/mt8173/bootblock.c
M src/soc/mediatek/mt8173/flash_controller.c
A src/soc/mediatek/mt8173/include/soc/dram_dma.h
M src/soc/mediatek/mt8173/mmu_operations.c
8 files changed, 105 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27349/1
diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c
index 1f56547..9f5ce5f 100644
--- a/src/mainboard/google/oak/romstage.c
+++ b/src/mainboard/google/oak/romstage.c
@@ -63,7 +63,7 @@
else
mt_pll_raise_ca53_freq(1700 * MHz);
- mt8173_mmu_after_dram();
+ mtk_mmu_after_dram();
/* should be called after memory init */
cbmem_initialize_empty();
diff --git a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h
similarity index 69%
rename from src/soc/mediatek/mt8173/include/soc/mmu_operations.h
rename to src/soc/mediatek/common/include/soc/mmu_operations.h
index 2428c42..687bb5c 100644
--- a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h
+++ b/src/soc/mediatek/common/include/soc/mmu_operations.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2015 MediaTek Inc.
+ * Copyright 2018 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
-#ifndef __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__
-#define __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__
+#ifndef __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__
+#define __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__
#include <arch/mmu.h>
@@ -29,11 +29,11 @@
extern unsigned char _esram_l2c[];
#define _sram_l2c_size (_esram_l2c - _sram_l2c)
-extern unsigned char _dram_dma[];
-extern unsigned char _edram_dma[];
-#define _dram_dma_size (_edram_dma - _dram_dma)
+void mtk_mmu_config_dram_dma(void);
+void mtk_disable_l2c_sram(void);
-void mt8173_mmu_init(void);
-void mt8173_mmu_after_dram(void);
+void mtk_mmu_init(void);
+void mtk_mmu_after_dram(void);
+void mtk_mmu_disable_l2c_sram(void);
-#endif //__SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__
+#endif
diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c
new file mode 100644
index 0000000..cb921f8
--- /dev/null
+++ b/src/soc/mediatek/common/mmu_operations.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/mmu.h>
+#include <compiler.h>
+#include <symbols.h>
+#include <soc/emi.h>
+#include <soc/mmu_operations.h>
+
+__weak void mtk_mmu_config_dram_dma(void) { /* do nothing */ }
+
+void mtk_mmu_init(void)
+{
+ mmu_init();
+
+ /* Set 0x0 to the end of 2GB dram address as device memory */
+ mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM);
+
+ /* SRAM is cached */
+ mmu_config_range(_sram, _sram_size, CACHED_MEM);
+
+ /* L2C SRAM is cached */
+ mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM);
+
+ /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */
+ mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
+
+ mmu_enable();
+}
+
+void mtk_mmu_after_dram(void)
+{
+ /* Map DRAM as cached now that it's up and running */
+ mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);
+
+ mtk_mmu_config_dram_dma();
+}
+
+void mtk_mmu_disable_l2c_sram(void)
+{
+ /* Unmap L2C SRAM so it can be reclaimed by L2 cache */
+ /* TODO: Implement true unmapping, and also use it for the zero-page! */
+ mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);
+
+ /* Careful: changing cache geometry while it's active is a bad idea! */
+ mmu_disable();
+
+ mtk_disable_l2c_sram();
+
+ /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */
+ mmu_enable();
+}
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index 56c966a..d661832 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -29,7 +29,7 @@
bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c
bootblock-y += ../common/wdt.c
-bootblock-y += mmu_operations.c
+bootblock-y += ../common/mmu_operations.c mmu_operations.c
################################################################################
@@ -58,7 +58,7 @@
romstage-y += pmic_wrap.c mt6391.c
romstage-y += memory.c
romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
-romstage-y += mmu_operations.c
+romstage-y += ../common/mmu_operations.c mmu_operations.c
romstage-y += rtc.c
################################################################################
diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c
index 7fe879c..efccc0b 100644
--- a/src/soc/mediatek/mt8173/bootblock.c
+++ b/src/soc/mediatek/mt8173/bootblock.c
@@ -29,7 +29,7 @@
/* post init pll */
mt_pll_post_init();
- mt8173_mmu_init();
+ mtk_mmu_init();
/* init watch dog, will disable AP watch dog */
mtk_wdt_init();
diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c
index f776885..6856dcd 100644
--- a/src/soc/mediatek/mt8173/flash_controller.c
+++ b/src/soc/mediatek/mt8173/flash_controller.c
@@ -25,8 +25,8 @@
#include <string.h>
#include <symbols.h>
#include <timer.h>
+#include <soc/dram_dma.h>
#include <soc/flash_controller.h>
-#include <soc/mmu_operations.h>
#define get_nth_byte(d, n) ((d >> (8 * n)) & 0xff)
diff --git a/src/soc/mediatek/mt8173/include/soc/dram_dma.h b/src/soc/mediatek/mt8173/include/soc/dram_dma.h
new file mode 100644
index 0000000..8e2d0a4
--- /dev/null
+++ b/src/soc/mediatek/mt8173/include/soc/dram_dma.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__
+#define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__
+
+extern unsigned char _dram_dma[];
+extern unsigned char _edram_dma[];
+#define _dram_dma_size (_edram_dma - _dram_dma)
+
+#endif
diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c
index c744d65..c66fb3a 100644
--- a/src/soc/mediatek/mt8173/mmu_operations.c
+++ b/src/soc/mediatek/mt8173/mmu_operations.c
@@ -15,55 +15,22 @@
#include <arch/io.h>
#include <arch/mmu.h>
-#include <console/console.h>
#include <symbols.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <soc/addressmap.h>
-#include <soc/emi.h>
+#include <soc/dram_dma.h>
#include <soc/infracfg.h>
#include <soc/mcucfg.h>
#include <soc/mmu_operations.h>
-void mt8173_mmu_init(void)
+void mtk_mmu_config_dram_dma(void)
{
- mmu_init();
-
- /* Set 0x0 to the end of 2GB dram address as device memory */
- mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM);
-
- /* SRAM is cached */
- mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM);
-
- /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */
- mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
-
- /* set ttb as secure */
- mmu_config_range(_ttb, _ttb_size, SECURE_MEM);
-
- mmu_enable();
+ mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM);
}
-void mt8173_mmu_after_dram(void)
+void mtk_disable_l2c_sram(void)
{
- /* Map DRAM as cached now that it's up and running */
- mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);
-
- /* Unmap L2C SRAM so it can be reclaimed by L2 cache */
- /* TODO: Implement true unmapping, and also use it for the zero-page! */
- mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);
-
- mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM);
-
- /* Careful: changing cache geometry while it's active is a bad idea! */
- mmu_disable();
-
/* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max
* available L2 cache for A53 in MT8173. */
write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8);
/* turn off the l2c sram clock */
write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN);
-
- /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */
- mmu_enable();
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f
Gerrit-Change-Number: 27349
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Hsieh <tristan.shieh at mediatek.com>
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