<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27349">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek: Share MMU operation code among similar SOCs<br><br>Refactor MMU operation code which will be reused among similar SOCs.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Elm<br><br>Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>M src/mainboard/google/oak/romstage.c<br>R src/soc/mediatek/common/include/soc/mmu_operations.h<br>A src/soc/mediatek/common/mmu_operations.c<br>M src/soc/mediatek/mt8173/Makefile.inc<br>M src/soc/mediatek/mt8173/bootblock.c<br>M src/soc/mediatek/mt8173/flash_controller.c<br>A src/soc/mediatek/mt8173/include/soc/dram_dma.h<br>M src/soc/mediatek/mt8173/mmu_operations.c<br>8 files changed, 105 insertions(+), 51 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27349/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c</span><br><span>index 1f56547..9f5ce5f 100644</span><br><span>--- a/src/mainboard/google/oak/romstage.c</span><br><span>+++ b/src/mainboard/google/oak/romstage.c</span><br><span>@@ -63,7 +63,7 @@</span><br><span> else</span><br><span> mt_pll_raise_ca53_freq(1700 * MHz);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- mt8173_mmu_after_dram();</span><br><span style="color: hsl(120, 100%, 40%);">+ mtk_mmu_after_dram();</span><br><span> </span><br><span> /* should be called after memory init */</span><br><span> cbmem_initialize_empty();</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h</span><br><span>similarity index 69%</span><br><span>rename from src/soc/mediatek/mt8173/include/soc/mmu_operations.h</span><br><span>rename to src/soc/mediatek/common/include/soc/mmu_operations.h</span><br><span>index 2428c42..687bb5c 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h</span><br><span>+++ b/src/soc/mediatek/common/include/soc/mmu_operations.h</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2015 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -13,8 +13,8 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__</span><br><span> </span><br><span> #include <arch/mmu.h></span><br><span> </span><br><span>@@ -29,11 +29,11 @@</span><br><span> extern unsigned char _esram_l2c[];</span><br><span> #define _sram_l2c_size (_esram_l2c - _sram_l2c)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-extern unsigned char _dram_dma[];</span><br><span style="color: hsl(0, 100%, 40%);">-extern unsigned char _edram_dma[];</span><br><span style="color: hsl(0, 100%, 40%);">-#define _dram_dma_size (_edram_dma - _dram_dma)</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_mmu_config_dram_dma(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_disable_l2c_sram(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void mt8173_mmu_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void mt8173_mmu_after_dram(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_mmu_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_mmu_after_dram(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_mmu_disable_l2c_sram(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#endif //__SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c</span><br><span>new file mode 100644</span><br><span>index 0000000..cb921f8</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/common/mmu_operations.c</span><br><span>@@ -0,0 +1,64 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/mmu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <compiler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <symbols.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mmu_operations.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void mtk_mmu_config_dram_dma(void) { /* do nothing */ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_mmu_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set 0x0 to the end of 2GB dram address as device memory */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SRAM is cached */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_sram, _sram_size, CACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* L2C SRAM is cached */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_enable();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_mmu_after_dram(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Map DRAM as cached now that it's up and running */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mtk_mmu_config_dram_dma();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_mmu_disable_l2c_sram(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Unmap L2C SRAM so it can be reclaimed by L2 cache */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Implement true unmapping, and also use it for the zero-page! */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Careful: changing cache geometry while it's active is a bad idea! */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_disable();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mtk_disable_l2c_sram();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_enable();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>index 56c966a..d661832 100644</span><br><span>--- a/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>@@ -29,7 +29,7 @@</span><br><span> </span><br><span> bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c</span><br><span> bootblock-y += ../common/wdt.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += mmu_operations.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../common/mmu_operations.c mmu_operations.c</span><br><span> </span><br><span> ################################################################################</span><br><span> </span><br><span>@@ -58,7 +58,7 @@</span><br><span> romstage-y += pmic_wrap.c mt6391.c</span><br><span> romstage-y += memory.c</span><br><span> romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += mmu_operations.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += ../common/mmu_operations.c mmu_operations.c</span><br><span> romstage-y += rtc.c</span><br><span> </span><br><span> ################################################################################</span><br><span>diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c</span><br><span>index 7fe879c..efccc0b 100644</span><br><span>--- a/src/soc/mediatek/mt8173/bootblock.c</span><br><span>+++ b/src/soc/mediatek/mt8173/bootblock.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> /* post init pll */</span><br><span> mt_pll_post_init();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- mt8173_mmu_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ mtk_mmu_init();</span><br><span> </span><br><span> /* init watch dog, will disable AP watch dog */</span><br><span> mtk_wdt_init();</span><br><span>diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c</span><br><span>index f776885..6856dcd 100644</span><br><span>--- a/src/soc/mediatek/mt8173/flash_controller.c</span><br><span>+++ b/src/soc/mediatek/mt8173/flash_controller.c</span><br><span>@@ -25,8 +25,8 @@</span><br><span> #include <string.h></span><br><span> #include <symbols.h></span><br><span> #include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dram_dma.h></span><br><span> #include <soc/flash_controller.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/mmu_operations.h></span><br><span> </span><br><span> #define get_nth_byte(d, n) ((d >> (8 * n)) & 0xff)</span><br><span> </span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/dram_dma.h b/src/soc/mediatek/mt8173/include/soc/dram_dma.h</span><br><span>new file mode 100644</span><br><span>index 0000000..8e2d0a4</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/dram_dma.h</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern unsigned char _dram_dma[];</span><br><span style="color: hsl(120, 100%, 40%);">+extern unsigned char _edram_dma[];</span><br><span style="color: hsl(120, 100%, 40%);">+#define _dram_dma_size (_edram_dma - _dram_dma)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c</span><br><span>index c744d65..c66fb3a 100644</span><br><span>--- a/src/soc/mediatek/mt8173/mmu_operations.c</span><br><span>+++ b/src/soc/mediatek/mt8173/mmu_operations.c</span><br><span>@@ -15,55 +15,22 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <arch/mmu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span> #include <symbols.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/addressmap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dram_dma.h></span><br><span> #include <soc/infracfg.h></span><br><span> #include <soc/mcucfg.h></span><br><span> #include <soc/mmu_operations.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void mt8173_mmu_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_mmu_config_dram_dma(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set 0x0 to the end of 2GB dram address as device memory */</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SRAM is cached */</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* set ttb as secure */</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_config_range(_ttb, _ttb_size, SECURE_MEM);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_enable();</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void mt8173_mmu_after_dram(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_disable_l2c_sram(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Map DRAM as cached now that it's up and running */</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Unmap L2C SRAM so it can be reclaimed by L2 cache */</span><br><span style="color: hsl(0, 100%, 40%);">- /* TODO: Implement true unmapping, and also use it for the zero-page! */</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Careful: changing cache geometry while it's active is a bad idea! */</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_disable();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max</span><br><span> * available L2 cache for A53 in MT8173. */</span><br><span> write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8);</span><br><span> /* turn off the l2c sram clock */</span><br><span> write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */</span><br><span style="color: hsl(0, 100%, 40%);">- mmu_enable();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27349">change 27349</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f </div>
<div style="display:none"> Gerrit-Change-Number: 27349 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>