[coreboot-gerrit] Change in coreboot[master]: [WIP]nb/intel/i945: Use C_ENVIRONMENT_BOOTBLOCK
Arthur Heymans (Code Review)
gerrit at coreboot.org
Mon Jan 29 23:00:30 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23496
Change subject: [WIP]nb/intel/i945: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
[WIP]nb/intel/i945: Use C_ENVIRONMENT_BOOTBLOCK
This currently gets to bootblock
Change-Id: I4a301c47f058b119f692ee1cff2e43414281a861
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/car/Makefile.inc
A src/cpu/intel/car/bootblock.c
M src/cpu/intel/car/cache_as_ram.S
M src/cpu/intel/car/romstage.c
M src/cpu/intel/car/teardown_car.S
M src/cpu/intel/socket_441/Kconfig
M src/mainboard/intel/d945gclf/Makefile.inc
A src/mainboard/intel/d945gclf/bootblock.c
M src/mainboard/intel/d945gclf/romstage.c
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/Makefile.inc
M src/northbridge/intel/i945/bootblock.c
M src/superio/smsc/lpc47m15x/Makefile.inc
13 files changed, 110 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/23496/1
diff --git a/src/cpu/intel/car/Makefile.inc b/src/cpu/intel/car/Makefile.inc
index 719972d..216b655 100644
--- a/src/cpu/intel/car/Makefile.inc
+++ b/src/cpu/intel/car/Makefile.inc
@@ -1,2 +1,7 @@
-cpu_incs-y += $(src)/cpu/intel/car/common_cache_as_ram.inc
postcar-y += teardown_car.S
+ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
+bootblock-y += cache_as_ram.S
+bootblock-y += bootblock.c
+else
+cpu_incs-y += $(src)/cpu/intel/car/common_cache_as_ram.inc
+endif
\ No newline at end of file
diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c
new file mode 100644
index 0000000..da9d0e3
--- /dev/null
+++ b/src/cpu/intel/car/bootblock.c
@@ -0,0 +1,7 @@
+#include <bootblock_common.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+ /* Call lib/bootblock.c main */
+ bootblock_main_with_timestamp(base_timestamp);
+}
diff --git a/src/cpu/intel/car/cache_as_ram.S b/src/cpu/intel/car/cache_as_ram.S
index be04f4f..d666ae6 100644
--- a/src/cpu/intel/car/cache_as_ram.S
+++ b/src/cpu/intel/car/cache_as_ram.S
@@ -19,6 +19,8 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
+.global bootblock_pre_c_entry
+
/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
* and the space used by the reference code. These 2 values combined should
* be a power of 2 because the MTRR setup assumes that. */
@@ -32,6 +34,7 @@
/* Save the BIST result. */
movl %eax, %ebp
+bootblock_pre_c_entry:
cache_as_ram:
post_code(0x20)
@@ -223,6 +226,22 @@
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0
+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+ /* Setup the stack. */
+ mov $_car_stack_end, %esp
+
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the two pushes below. */
+ andl $0xfffffff0, %esp
+ sub $8, %esp
+
+ /*push TSC value to stack*/
+ movd %mm2, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm1, %eax
+ pushl %eax /* tsc[31:0] */
+
+#else
/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
@@ -231,7 +250,14 @@
movl %ebp, %eax
movl %esp, %ebp
pushl %eax
+#endif
+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+ post_code(0x29)
+ call bootblock_c_entry
+ /* Should never be reached */
+ jmp .Lhlt
+#else
before_romstage:
post_code(0x29)
/* Call romstage.c main function. */
@@ -366,6 +392,8 @@
cld /* Clear direction flag. */
call romstage_after_car
+#endif /* IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) */
+
postcar_entry_failure:
.Lhlt:
post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 555c384..54efa8c 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -58,6 +58,15 @@
return romstage_stack_after_car;
}
+asmlinkage void car_stage_entry(void)
+{
+ unsigned long bist = 0;
+ console_init();
+ mainboard_romstage_entry(bist);
+ setup_stack_and_mtrrs();
+}
+
+
asmlinkage void romstage_after_car(void)
{
/* Load the ramstage. */
diff --git a/src/cpu/intel/car/teardown_car.S b/src/cpu/intel/car/teardown_car.S
index 63c56ac..5c06a7c 100644
--- a/src/cpu/intel/car/teardown_car.S
+++ b/src/cpu/intel/car/teardown_car.S
@@ -41,7 +41,7 @@
/* Disable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- andl $(~MTRR_DEF_TYPE_EN), %eax
+ and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
wrmsr
#if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE)
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index b157f62..59808a6 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -18,4 +18,11 @@
hex
default 0x8000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x4000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
+
endif # CPU_INTEL_SOCKET_441
diff --git a/src/mainboard/intel/d945gclf/Makefile.inc b/src/mainboard/intel/d945gclf/Makefile.inc
index f3d7e76..d9af68a 100644
--- a/src/mainboard/intel/d945gclf/Makefile.inc
+++ b/src/mainboard/intel/d945gclf/Makefile.inc
@@ -1,2 +1,4 @@
ramstage-y += cstates.c
romstage-y += gpio.c
+
+bootblock-y += bootblock.c
\ No newline at end of file
diff --git a/src/mainboard/intel/d945gclf/bootblock.c b/src/mainboard/intel/d945gclf/bootblock.c
new file mode 100644
index 0000000..7173874
--- /dev/null
+++ b/src/mainboard/intel/d945gclf/bootblock.c
@@ -0,0 +1,8 @@
+#include <bootblock_common.h>
+#include <superio/smsc/lpc47m15x/lpc47m15x.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)
+
+void bootblock_mainboard_early_init(void) {
+ lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
+}
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 27c1e3e..404319a 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -147,7 +147,7 @@
lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
/* Set up the console */
- console_init();
+// console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index e04d0c3..b81a285 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -30,6 +30,8 @@
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select POSTCAR_STAGE
select POSTCAR_CONSOLE
+ select C_ENVIRONMENT_BOOTBLOCK
+ select BOOTBLOCK_CONSOLE
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index ffeabdc..47fb40f 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y)
+bootblock-y += bootblock.c
+
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 4c3c90c..a063389 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -1,9 +1,23 @@
#include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include "i945.h"
-/* Just re-define this instead of including i945.h. It blows up romcc. */
-#define PCIEXBAR 0x48
-static void bootblock_northbridge_init(void)
+static void enable_spi_prefetch(void)
+{
+ u8 reg8;
+ pci_devfn_t dev;
+
+ dev = PCI_DEV(0, 0x1f, 0);
+
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+void bootblock_soc_early_init(void)
{
uint32_t reg;
@@ -21,4 +35,23 @@
*/
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
+
+ enable_spi_prefetch();
+
+ /* Enable RCBA */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
+
+ /* Enable Serial IRQ */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
+ /*
+ * enable COMA and COMB decode range.
+ * Can always be changed in mainboard romstage
+ */
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
+ u16 lpc_en = pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_EN);
+ lpc_en |= CNF2_LPC_EN | CNF1_LPC_EN | COMB_LPC_EN | COMA_LPC_EN;
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, lpc_en);
}
diff --git a/src/superio/smsc/lpc47m15x/Makefile.inc b/src/superio/smsc/lpc47m15x/Makefile.inc
index f465669..dc6b9ab 100644
--- a/src/superio/smsc/lpc47m15x/Makefile.inc
+++ b/src/superio/smsc/lpc47m15x/Makefile.inc
@@ -13,5 +13,6 @@
## GNU General Public License for more details.
##
+bootblock-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c
romstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.c
--
To view, visit https://review.coreboot.org/23496
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4a301c47f058b119f692ee1cff2e43414281a861
Gerrit-Change-Number: 23496
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180129/a8716f57/attachment-0001.html>
More information about the coreboot-gerrit
mailing list