<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23496">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]nb/intel/i945: Use C_ENVIRONMENT_BOOTBLOCK<br><br>This currently gets to bootblock<br><br>Change-Id: I4a301c47f058b119f692ee1cff2e43414281a861<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/car/Makefile.inc<br>A src/cpu/intel/car/bootblock.c<br>M src/cpu/intel/car/cache_as_ram.S<br>M src/cpu/intel/car/romstage.c<br>M src/cpu/intel/car/teardown_car.S<br>M src/cpu/intel/socket_441/Kconfig<br>M src/mainboard/intel/d945gclf/Makefile.inc<br>A src/mainboard/intel/d945gclf/bootblock.c<br>M src/mainboard/intel/d945gclf/romstage.c<br>M src/northbridge/intel/i945/Kconfig<br>M src/northbridge/intel/i945/Makefile.inc<br>M src/northbridge/intel/i945/bootblock.c<br>M src/superio/smsc/lpc47m15x/Makefile.inc<br>13 files changed, 110 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/23496/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/Makefile.inc b/src/cpu/intel/car/Makefile.inc</span><br><span>index 719972d..216b655 100644</span><br><span>--- a/src/cpu/intel/car/Makefile.inc</span><br><span>+++ b/src/cpu/intel/car/Makefile.inc</span><br><span>@@ -1,2 +1,7 @@</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_incs-y += $(src)/cpu/intel/car/common_cache_as_ram.inc</span><br><span> postcar-y += teardown_car.S</span><br><span style="color: hsl(120, 100%, 40%);">+ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += cache_as_ram.S</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+else</span><br><span style="color: hsl(120, 100%, 40%);">+cpu_incs-y += $(src)/cpu/intel/car/common_cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..da9d0e3</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/car/bootblock.c</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+     /* Call lib/bootblock.c main */</span><br><span style="color: hsl(120, 100%, 40%);">+       bootblock_main_with_timestamp(base_timestamp);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/cpu/intel/car/cache_as_ram.S b/src/cpu/intel/car/cache_as_ram.S</span><br><span>index be04f4f..d666ae6 100644</span><br><span>--- a/src/cpu/intel/car/cache_as_ram.S</span><br><span>+++ b/src/cpu/intel/car/cache_as_ram.S</span><br><span>@@ -19,6 +19,8 @@</span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/post_code.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+.global bootblock_pre_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* The full cache-as-ram size includes the cache-as-ram portion from coreboot</span><br><span>  * and the space used by the reference code. These 2 values combined should</span><br><span>  * be a power of 2 because the MTRR setup assumes that. */</span><br><span>@@ -32,6 +34,7 @@</span><br><span>        /* Save the BIST result. */</span><br><span>  movl    %eax, %ebp</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock_pre_c_entry:</span><br><span> cache_as_ram:</span><br><span>      post_code(0x20)</span><br><span> </span><br><span>@@ -223,6 +226,22 @@</span><br><span>   andl    $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span>    movl    %eax, %cr0</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)</span><br><span style="color: hsl(120, 100%, 40%);">+        /* Setup the stack. */</span><br><span style="color: hsl(120, 100%, 40%);">+        mov     $_car_stack_end, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+       /* Need to align stack to 16 bytes at call instruction. Account for</span><br><span style="color: hsl(120, 100%, 40%);">+   the two pushes below. */</span><br><span style="color: hsl(120, 100%, 40%);">+      andl    $0xfffffff0, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+     sub     $8, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    /*push TSC value to stack*/</span><br><span style="color: hsl(120, 100%, 40%);">+   movd    %mm2, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+    pushl   %eax    /* tsc[63:32] */</span><br><span style="color: hsl(120, 100%, 40%);">+      movd    %mm1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+    pushl   %eax    /* tsc[31:0] */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span>     /* Setup the stack. */</span><br><span>       movl    $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax</span><br><span>     movl    %eax, %esp</span><br><span>@@ -231,7 +250,14 @@</span><br><span>    movl    %ebp, %eax</span><br><span>   movl    %esp, %ebp</span><br><span>   pushl   %eax</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)</span><br><span style="color: hsl(120, 100%, 40%);">+      post_code(0x29)</span><br><span style="color: hsl(120, 100%, 40%);">+       call    bootblock_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+     /* Should never be reached */</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp     .Lhlt</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> before_romstage:</span><br><span>     post_code(0x29)</span><br><span>      /* Call romstage.c main function. */</span><br><span>@@ -366,6 +392,8 @@</span><br><span>   cld                     /* Clear direction flag. */</span><br><span>  call    romstage_after_car</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> postcar_entry_failure:</span><br><span> .Lhlt:</span><br><span>        post_code(POST_DEAD_CODE)</span><br><span>diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c</span><br><span>index 555c384..54efa8c 100644</span><br><span>--- a/src/cpu/intel/car/romstage.c</span><br><span>+++ b/src/cpu/intel/car/romstage.c</span><br><span>@@ -58,6 +58,15 @@</span><br><span>  return romstage_stack_after_car;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void car_stage_entry(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+   unsigned long bist = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+       console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+       mainboard_romstage_entry(bist);</span><br><span style="color: hsl(120, 100%, 40%);">+        setup_stack_and_mtrrs();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> asmlinkage void romstage_after_car(void)</span><br><span> {</span><br><span>    /* Load the ramstage. */</span><br><span>diff --git a/src/cpu/intel/car/teardown_car.S b/src/cpu/intel/car/teardown_car.S</span><br><span>index 63c56ac..5c06a7c 100644</span><br><span>--- a/src/cpu/intel/car/teardown_car.S</span><br><span>+++ b/src/cpu/intel/car/teardown_car.S</span><br><span>@@ -41,7 +41,7 @@</span><br><span>    /* Disable MTRR. */</span><br><span>  movl    $MTRR_DEF_TYPE_MSR, %ecx</span><br><span>     rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">-   andl    $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+    and     $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax</span><br><span>  wrmsr</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE)</span><br><span>diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig</span><br><span>index b157f62..59808a6 100644</span><br><span>--- a/src/cpu/intel/socket_441/Kconfig</span><br><span>+++ b/src/cpu/intel/socket_441/Kconfig</span><br><span>@@ -18,4 +18,11 @@</span><br><span>  hex</span><br><span>  default 0x8000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DCACHE_BSP_STACK_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+      hex</span><br><span style="color: hsl(120, 100%, 40%);">+   default 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+        help</span><br><span style="color: hsl(120, 100%, 40%);">+    The amount of anticipated stack usage in CAR by bootblock and</span><br><span style="color: hsl(120, 100%, 40%);">+         other stages.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif # CPU_INTEL_SOCKET_441</span><br><span>diff --git a/src/mainboard/intel/d945gclf/Makefile.inc b/src/mainboard/intel/d945gclf/Makefile.inc</span><br><span>index f3d7e76..d9af68a 100644</span><br><span>--- a/src/mainboard/intel/d945gclf/Makefile.inc</span><br><span>+++ b/src/mainboard/intel/d945gclf/Makefile.inc</span><br><span>@@ -1,2 +1,4 @@</span><br><span> ramstage-y += cstates.c</span><br><span> romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/intel/d945gclf/bootblock.c b/src/mainboard/intel/d945gclf/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..7173874</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/d945gclf/bootblock.c</span><br><span>@@ -0,0 +1,8 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/smsc/lpc47m15x/lpc47m15x.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_mainboard_early_init(void) {</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c</span><br><span>index 27c1e3e..404319a 100644</span><br><span>--- a/src/mainboard/intel/d945gclf/romstage.c</span><br><span>+++ b/src/mainboard/intel/d945gclf/romstage.c</span><br><span>@@ -147,7 +147,7 @@</span><br><span>        lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */</span><br><span> </span><br><span>      /* Set up the console */</span><br><span style="color: hsl(0, 100%, 40%);">-        console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+//     console_init();</span><br><span> </span><br><span>  /* Halt if there was a built in self test failure */</span><br><span>         report_bist_failure(bist);</span><br><span>diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig</span><br><span>index e04d0c3..b81a285 100644</span><br><span>--- a/src/northbridge/intel/i945/Kconfig</span><br><span>+++ b/src/northbridge/intel/i945/Kconfig</span><br><span>@@ -30,6 +30,8 @@</span><br><span>  select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span>     select POSTCAR_STAGE</span><br><span>         select POSTCAR_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+        select C_ENVIRONMENT_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+        select BOOTBLOCK_CONSOLE</span><br><span> </span><br><span> config NORTHBRIDGE_INTEL_SUBTYPE_I945GC</span><br><span>      def_bool n</span><br><span>diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc</span><br><span>index ffeabdc..47fb40f 100644</span><br><span>--- a/src/northbridge/intel/i945/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/i945/Makefile.inc</span><br><span>@@ -15,6 +15,8 @@</span><br><span> </span><br><span> ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ramstage-y += ram_calc.c</span><br><span> ramstage-y += northbridge.c</span><br><span> ramstage-y += gma.c</span><br><span>diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c</span><br><span>index 4c3c90c..a063389 100644</span><br><span>--- a/src/northbridge/intel/i945/bootblock.c</span><br><span>+++ b/src/northbridge/intel/i945/bootblock.c</span><br><span>@@ -1,9 +1,23 @@</span><br><span> #include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "i945.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Just re-define this instead of including i945.h. It blows up romcc. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCIEXBAR   0x48</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void bootblock_northbridge_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_spi_prefetch(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+        u8 reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+      pci_devfn_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    dev = PCI_DEV(0, 0x1f, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+  reg8 = pci_read_config8(dev, 0xdc);</span><br><span style="color: hsl(120, 100%, 40%);">+   reg8 &= ~(3 << 2);</span><br><span style="color: hsl(120, 100%, 40%);">+  reg8 |= (2 << 2); /* Prefetching and Caching Enabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, 0xdc, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_early_init(void)</span><br><span> {</span><br><span>   uint32_t reg;</span><br><span> </span><br><span>@@ -21,4 +35,23 @@</span><br><span>        */</span><br><span>  reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */</span><br><span>  pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+     enable_spi_prefetch();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+      /* Enable RCBA */</span><br><span style="color: hsl(120, 100%, 40%);">+     pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable upper 128bytes of CMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+   RCBA32(0x3400) = (1 << 2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    /* Enable Serial IRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+       pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+    /*</span><br><span style="color: hsl(120, 100%, 40%);">+     * enable COMA and COMB decode range.</span><br><span style="color: hsl(120, 100%, 40%);">+  * Can always be changed in mainboard romstage</span><br><span style="color: hsl(120, 100%, 40%);">+         */</span><br><span style="color: hsl(120, 100%, 40%);">+   pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+  u16 lpc_en = pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+  lpc_en |= CNF2_LPC_EN | CNF1_LPC_EN | COMB_LPC_EN | COMA_LPC_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+      pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, lpc_en);</span><br><span> }</span><br><span>diff --git a/src/superio/smsc/lpc47m15x/Makefile.inc b/src/superio/smsc/lpc47m15x/Makefile.inc</span><br><span>index f465669..dc6b9ab 100644</span><br><span>--- a/src/superio/smsc/lpc47m15x/Makefile.inc</span><br><span>+++ b/src/superio/smsc/lpc47m15x/Makefile.inc</span><br><span>@@ -13,5 +13,6 @@</span><br><span> ## GNU General Public License for more details.</span><br><span> ##</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c</span><br><span> romstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c</span><br><span> ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23496">change 23496</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23496"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4a301c47f058b119f692ee1cff2e43414281a861 </div>
<div style="display:none"> Gerrit-Change-Number: 23496 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>