[coreboot-gerrit] Change in coreboot[master]: [WIP]nb/intel/gm45: Use TSEG for SMM
Arthur Heymans (Code Review)
gerrit at coreboot.org
Thu Jan 25 00:34:34 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23419
Change subject: [WIP]nb/intel/gm45: Use TSEG for SMM
......................................................................
[WIP]nb/intel/gm45: Use TSEG for SMM
fully not working (yet)!
Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/model_1067x/Makefile.inc
M src/cpu/intel/model_1067x/model_1067x_init.c
M src/cpu/intel/smm/gen1/smi.h
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/ram_calc.c
M src/northbridge/intel/nehalem/northbridge.c
M src/southbridge/intel/i82801ix/Makefile.inc
M src/southbridge/intel/i82801ix/smi.c
M src/southbridge/intel/i82801ix/smihandler.c
12 files changed, 74 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23419/1
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index 3e6cb2c..133c9cf 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,5 +1,6 @@
ramstage-y += model_1067x_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 0d9169b..37ccdf4 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -28,6 +28,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/common/common.h>
+#include <cpu/intel/smm/gen1/smi.h>
#include "chip.h"
static void init_timer(void)
@@ -318,6 +319,22 @@
intel_sibling_init(cpu);
}
+int cpu_get_apic_id_map(int *apic_id_map)
+{
+ unsigned int i;
+
+ /* Logical processors (threads) per core */
+ const struct cpuid_result cpuid1 = cpuid(1);
+ /* Read number of cores. */
+ const char cores = (cpuid1.ebx >> 16) & 0xf;
+
+ /* TODO in parallel MP cpuid(1).ebx */
+ for (i = 0; i < cores; i++)
+ apic_id_map[i] = i;
+
+ return cores;
+}
+
static struct device_operations cpu_dev_ops = {
.init = model_1067x_init,
};
diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
index c328eae..f4cbbc3 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/cpu/intel/smm/gen1/smi.h
@@ -16,5 +16,6 @@
void southbridge_trigger_smi(void);
void southbridge_clear_smi_status(void);
u32 northbridge_get_tseg_base(void);
+u32 northbridge_get_tseg_size(void);
int cpu_get_apic_id_map(int *apic_id_map);
void northbridge_write_smram(u8 smram);
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index da43de0..8026a52 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -123,7 +123,7 @@
/* TSEG base is usually aligned down (to 8MiB). So we can't
derive the TSEG size from the distance to GTT but use the
configuration value instead. */
- const u32 tseg_size = CONFIG_SMM_TSEG_SIZE;
+ const u32 tseg_size = northbridge_get_tseg_size();
/* The SMRAM available to the handler is 4MiB
since the IEDRAM lives at TSEGMB + 4MiB. */
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 85902d3..cd41371 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -29,6 +29,7 @@
select RELOCATABLE_RAMSTAGE
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+ select SMM_TSEG
config CBFS_SIZE
hex
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index a71fa89..8bc7d7d 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -434,6 +434,7 @@
u32 decode_igd_memory_size(u32 gms);
u32 decode_igd_gtt_size(u32 gsm);
u32 decode_tseg_size(const u8 esmramc);
+uintptr_t smm_region_start(void);
void init_iommu(void);
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 2b36c70..d937ece 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -25,6 +25,7 @@
#include <boot/tables.h>
#include <arch/acpi.h>
#include <cbmem.h>
+#include <cpu/intel/smm/gen1/smi.h>
#include "chip.h"
#include "gm45.h"
#include "arch/acpi.h"
@@ -191,6 +192,23 @@
pci_write_config32(dev, PCI_COMMAND, reg32);
}
+u32 northbridge_get_tseg_base(void)
+{
+ return (u32)smm_region_start();
+}
+
+u32 northbridge_get_tseg_size(void)
+{
+ const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)),
+ D0F0_ESMRAMC);
+ return decode_tseg_size(esmramc) << 10;
+}
+
+void northbridge_write_smram(u8 smram)
+{
+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_SMRAM, smram);
+}
+
static struct device_operations pci_domain_ops = {
.read_resources = mch_domain_read_resources,
.set_resources = mch_domain_set_resources,
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index d619308..b7812cd 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -82,7 +82,7 @@
}
}
-static uintptr_t smm_region_start(void)
+uintptr_t smm_region_start(void)
{
const pci_devfn_t dev = PCI_DEV(0, 0, 0);
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index b09460c..158415f 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -161,6 +161,12 @@
return pci_read_config32(dev, TSEG) & ~1;
}
+u32 northbridge_get_tseg_size(void)
+{
+ return CONFIG_TSEG_SIZE;
+}
+
+
static void mc_set_resources(device_t dev)
{
/* And call the normal set_resources */
diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc
index e563cfc..7f30a0b 100644
--- a/src/southbridge/intel/i82801ix/Makefile.inc
+++ b/src/southbridge/intel/i82801ix/Makefile.inc
@@ -33,7 +33,6 @@
ramstage-y += ../i82801gx/watchdog.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += early_init.c
diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c
index bf3aa6b..338ec73 100644
--- a/src/southbridge/intel/i82801ix/smi.c
+++ b/src/southbridge/intel/i82801ix/smi.c
@@ -25,6 +25,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <string.h>
+#include <cpu/intel/smm/gen1/smi.h>
#include "i82801ix.h"
/* I945/GM45 */
@@ -233,9 +234,6 @@
outb(reg8, pmbase + SMI_EN);
}
-extern uint8_t smm_relocation_start, smm_relocation_end;
-static void *default_smm_area = NULL;
-
static void smm_relocate(void)
{
u32 smi_en;
@@ -252,13 +250,6 @@
return;
}
- default_smm_area = backup_default_smm_area();
-
- /* copy the SMM relocation code */
- memcpy((void *)0x38000, &smm_relocation_start,
- &smm_relocation_end - &smm_relocation_start);
- wbinvd();
-
printk(BIOS_DEBUG, "\n");
dump_smi_status(reset_smi_status());
dump_pm1_status(reset_pm1_status());
@@ -295,7 +286,10 @@
pm1_en |= PWRBTN_EN;
pm1_en |= GBL_EN;
outw(pm1_en, pmbase + PM1_EN);
+}
+void southbridge_trigger_smi(void)
+{
/**
* There are several methods of raising a controlled SMI# via
* software, among them:
@@ -314,42 +308,8 @@
outb(0x00, 0xb2);
}
-static int smm_handler_copied = 0;
-
-static void smm_install(void)
+void southbridge_smm_init(void)
{
- /* The first CPU running this gets to copy the SMM handler. But not all
- * of them.
- */
- if (smm_handler_copied)
- return;
- smm_handler_copied = 1;
-
-
- /* if we're resuming from S3, the SMM code is already in place,
- * so don't copy it again to keep the current SMM state */
-
- if (!acpi_is_wakeup_s3()) {
- /* enable the SMM memory window */
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
- D_OPEN | G_SMRAME | C_BASE_SEG);
-
- /* copy the real SMM handler */
- memcpy((void *)0xa0000, _binary_smm_start,
- _binary_smm_end - _binary_smm_start);
- wbinvd();
- }
-
- /* close the SMM memory window and enable normal SMM */
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
- G_SMRAME | C_BASE_SEG);
-}
-
-void smm_init(void)
-{
- /* Put SMM code to 0xa0000 */
- smm_install();
-
/* Put relocation code to 0x38000 and relocate SMBASE */
smm_relocate();
@@ -357,22 +317,6 @@
smi_set_eos();
}
-void smm_init_completion(void)
-{
- restore_default_smm_area(default_smm_area);
-}
-
-void smm_lock(void)
-{
- /* LOCK the SMM memory window and enable normal SMM.
- * After running this function, only a full reset can
- * make the SMM registers writable again.
- */
- printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
- D_LCK | G_SMRAME | C_BASE_SEG);
-}
-
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
/* The GDT or coreboot table is going to live here. But a long time
@@ -383,3 +327,15 @@
*(u32 *)0x508 = (u32)smi1;
outb(APM_CNT_GNVS_UPDATE, 0xb2);
}
+
+void southbridge_clear_smi_status(void)
+{
+ /* Clear SMI status */
+ reset_smi_status();
+
+ /* Clear PM1 status */
+ reset_pm1_status();
+
+ /* Set EOS bit so other SMIs can occur. */
+ smi_set_eos();
+}
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 7ad00ed..00b6d28 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -222,7 +222,7 @@
outb(reg8, pmbase + SMI_EN);
}
-static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_apmc(void)
{
u32 pmctrl;
u8 reg8;
@@ -276,7 +276,7 @@
}
}
-static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_pm1(void)
{
u16 pm1_sts;
volatile u8 cmos_status;
@@ -301,7 +301,7 @@
}
}
-static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_gpe0(void)
{
u32 gpe0_sts;
@@ -309,7 +309,7 @@
dump_gpe0_status(gpe0_sts);
}
-static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_gpi(void)
{
u16 reg16;
reg16 = inw(pmbase + ALT_GP_SMI_STS);
@@ -324,7 +324,7 @@
}
-static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_tco(void)
{
u32 tco_sts;
@@ -362,13 +362,13 @@
}
#if DEBUG_PERIODIC_SMIS
-static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_periodic(void)
{
printk(BIOS_DEBUG, "Periodic SMI.\n");
}
#endif
-static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_monitor(void)
{
#define IOTRAP(x) (trap_sts & (1 << x))
u32 trap_sts, trap_cycle;
@@ -422,8 +422,7 @@
#undef IOTRAP
}
-typedef void (*smi_handler_t)(unsigned int node,
- smm_state_save_area_t *state_save);
+typedef void (*smi_handler_t)(void);
smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
@@ -489,7 +488,7 @@
* @param node
* @param *state_save
*/
-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+void southbridge_smi_handler(void)
{
int i, dump = 0;
u32 smi_sts;
@@ -509,7 +508,7 @@
for (i = 0; i < 31; i++) {
if (smi_sts & (1 << i)) {
if (southbridge_smi[i])
- southbridge_smi[i](node, state_save);
+ southbridge_smi[i]();
else {
printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98
Gerrit-Change-Number: 23419
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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