<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23419">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]nb/intel/gm45: Use TSEG for SMM<br><br>fully not working (yet)!<br><br>Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_1067x/Makefile.inc<br>M src/cpu/intel/model_1067x/model_1067x_init.c<br>M src/cpu/intel/smm/gen1/smi.h<br>M src/cpu/intel/smm/gen1/smmrelocate.c<br>M src/northbridge/intel/gm45/Kconfig<br>M src/northbridge/intel/gm45/gm45.h<br>M src/northbridge/intel/gm45/northbridge.c<br>M src/northbridge/intel/gm45/ram_calc.c<br>M src/northbridge/intel/nehalem/northbridge.c<br>M src/southbridge/intel/i82801ix/Makefile.inc<br>M src/southbridge/intel/i82801ix/smi.c<br>M src/southbridge/intel/i82801ix/smihandler.c<br>12 files changed, 74 insertions(+), 75 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23419/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc</span><br><span>index 3e6cb2c..133c9cf 100644</span><br><span>--- a/src/cpu/intel/model_1067x/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_1067x/Makefile.inc</span><br><span>@@ -1,5 +1,6 @@</span><br><span> ramstage-y += model_1067x_init.c</span><br><span> subdirs-y += ../../x86/name</span><br><span> subdirs-y += ../common</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>index 0d9169b..37ccdf4 100644</span><br><span>--- a/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>+++ b/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>@@ -28,6 +28,7 @@</span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/name.h></span><br><span> #include <cpu/intel/common/common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/smm/gen1/smi.h></span><br><span> #include "chip.h"</span><br><span> </span><br><span> static void init_timer(void)</span><br><span>@@ -318,6 +319,22 @@</span><br><span> intel_sibling_init(cpu);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+int cpu_get_apic_id_map(int *apic_id_map)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Logical processors (threads) per core */</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cpuid_result cpuid1 = cpuid(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read number of cores. */</span><br><span style="color: hsl(120, 100%, 40%);">+ const char cores = (cpuid1.ebx >> 16) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO in parallel MP cpuid(1).ebx */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < cores; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ apic_id_map[i] = i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return cores;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static struct device_operations cpu_dev_ops = {</span><br><span> .init = model_1067x_init,</span><br><span> };</span><br><span>diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h</span><br><span>index c328eae..f4cbbc3 100644</span><br><span>--- a/src/cpu/intel/smm/gen1/smi.h</span><br><span>+++ b/src/cpu/intel/smm/gen1/smi.h</span><br><span>@@ -16,5 +16,6 @@</span><br><span> void southbridge_trigger_smi(void);</span><br><span> void southbridge_clear_smi_status(void);</span><br><span> u32 northbridge_get_tseg_base(void);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_size(void);</span><br><span> int cpu_get_apic_id_map(int *apic_id_map);</span><br><span> void northbridge_write_smram(u8 smram);</span><br><span>diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>index da43de0..8026a52 100644</span><br><span>--- a/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>+++ b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>@@ -123,7 +123,7 @@</span><br><span> /* TSEG base is usually aligned down (to 8MiB). So we can't</span><br><span> derive the TSEG size from the distance to GTT but use the</span><br><span> configuration value instead. */</span><br><span style="color: hsl(0, 100%, 40%);">- const u32 tseg_size = CONFIG_SMM_TSEG_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 tseg_size = northbridge_get_tseg_size();</span><br><span> </span><br><span> /* The SMRAM available to the handler is 4MiB</span><br><span> since the IEDRAM lives at TSEGMB + 4MiB. */</span><br><span>diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig</span><br><span>index 85902d3..cd41371 100644</span><br><span>--- a/src/northbridge/intel/gm45/Kconfig</span><br><span>+++ b/src/northbridge/intel/gm45/Kconfig</span><br><span>@@ -29,6 +29,7 @@</span><br><span> select RELOCATABLE_RAMSTAGE</span><br><span> select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SMM_TSEG</span><br><span> </span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span>diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h</span><br><span>index a71fa89..8bc7d7d 100644</span><br><span>--- a/src/northbridge/intel/gm45/gm45.h</span><br><span>+++ b/src/northbridge/intel/gm45/gm45.h</span><br><span>@@ -434,6 +434,7 @@</span><br><span> u32 decode_igd_memory_size(u32 gms);</span><br><span> u32 decode_igd_gtt_size(u32 gsm);</span><br><span> u32 decode_tseg_size(const u8 esmramc);</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t smm_region_start(void);</span><br><span> </span><br><span> void init_iommu(void);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c</span><br><span>index 2b36c70..d937ece 100644</span><br><span>--- a/src/northbridge/intel/gm45/northbridge.c</span><br><span>+++ b/src/northbridge/intel/gm45/northbridge.c</span><br><span>@@ -25,6 +25,7 @@</span><br><span> #include <boot/tables.h></span><br><span> #include <arch/acpi.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/smm/gen1/smi.h></span><br><span> #include "chip.h"</span><br><span> #include "gm45.h"</span><br><span> #include "arch/acpi.h"</span><br><span>@@ -191,6 +192,23 @@</span><br><span> pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return (u32)smm_region_start();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_size(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)),</span><br><span style="color: hsl(120, 100%, 40%);">+ D0F0_ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+ return decode_tseg_size(esmramc) << 10;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void northbridge_write_smram(u8 smram)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_SMRAM, smram);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static struct device_operations pci_domain_ops = {</span><br><span> .read_resources = mch_domain_read_resources,</span><br><span> .set_resources = mch_domain_set_resources,</span><br><span>diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>index d619308..b7812cd 100644</span><br><span>--- a/src/northbridge/intel/gm45/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>@@ -82,7 +82,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uintptr_t smm_region_start(void)</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t smm_region_start(void)</span><br><span> {</span><br><span> const pci_devfn_t dev = PCI_DEV(0, 0, 0);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c</span><br><span>index b09460c..158415f 100644</span><br><span>--- a/src/northbridge/intel/nehalem/northbridge.c</span><br><span>+++ b/src/northbridge/intel/nehalem/northbridge.c</span><br><span>@@ -161,6 +161,12 @@</span><br><span> return pci_read_config32(dev, TSEG) & ~1;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_size(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return CONFIG_TSEG_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void mc_set_resources(device_t dev)</span><br><span> {</span><br><span> /* And call the normal set_resources */</span><br><span>diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc</span><br><span>index e563cfc..7f30a0b 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/i82801ix/Makefile.inc</span><br><span>@@ -33,7 +33,6 @@</span><br><span> ramstage-y += ../i82801gx/watchdog.c</span><br><span> </span><br><span> ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span> </span><br><span> romstage-y += early_init.c</span><br><span>diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c</span><br><span>index bf3aa6b..338ec73 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/smi.c</span><br><span>+++ b/src/southbridge/intel/i82801ix/smi.c</span><br><span>@@ -25,6 +25,7 @@</span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/smm/gen1/smi.h></span><br><span> #include "i82801ix.h"</span><br><span> </span><br><span> /* I945/GM45 */</span><br><span>@@ -233,9 +234,6 @@</span><br><span> outb(reg8, pmbase + SMI_EN);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-extern uint8_t smm_relocation_start, smm_relocation_end;</span><br><span style="color: hsl(0, 100%, 40%);">-static void *default_smm_area = NULL;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void smm_relocate(void)</span><br><span> {</span><br><span> u32 smi_en;</span><br><span>@@ -252,13 +250,6 @@</span><br><span> return;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- default_smm_area = backup_default_smm_area();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* copy the SMM relocation code */</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy((void *)0x38000, &smm_relocation_start,</span><br><span style="color: hsl(0, 100%, 40%);">- &smm_relocation_end - &smm_relocation_start);</span><br><span style="color: hsl(0, 100%, 40%);">- wbinvd();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> printk(BIOS_DEBUG, "\n");</span><br><span> dump_smi_status(reset_smi_status());</span><br><span> dump_pm1_status(reset_pm1_status());</span><br><span>@@ -295,7 +286,10 @@</span><br><span> pm1_en |= PWRBTN_EN;</span><br><span> pm1_en |= GBL_EN;</span><br><span> outw(pm1_en, pmbase + PM1_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_trigger_smi(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span> /**</span><br><span> * There are several methods of raising a controlled SMI# via</span><br><span> * software, among them:</span><br><span>@@ -314,42 +308,8 @@</span><br><span> outb(0x00, 0xb2);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int smm_handler_copied = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void smm_install(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_smm_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* The first CPU running this gets to copy the SMM handler. But not all</span><br><span style="color: hsl(0, 100%, 40%);">- * of them.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- if (smm_handler_copied)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- smm_handler_copied = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* if we're resuming from S3, the SMM code is already in place,</span><br><span style="color: hsl(0, 100%, 40%);">- * so don't copy it again to keep the current SMM state */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!acpi_is_wakeup_s3()) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* enable the SMM memory window */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,</span><br><span style="color: hsl(0, 100%, 40%);">- D_OPEN | G_SMRAME | C_BASE_SEG);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* copy the real SMM handler */</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy((void *)0xa0000, _binary_smm_start,</span><br><span style="color: hsl(0, 100%, 40%);">- _binary_smm_end - _binary_smm_start);</span><br><span style="color: hsl(0, 100%, 40%);">- wbinvd();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* close the SMM memory window and enable normal SMM */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,</span><br><span style="color: hsl(0, 100%, 40%);">- G_SMRAME | C_BASE_SEG);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Put SMM code to 0xa0000 */</span><br><span style="color: hsl(0, 100%, 40%);">- smm_install();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Put relocation code to 0x38000 and relocate SMBASE */</span><br><span> smm_relocate();</span><br><span> </span><br><span>@@ -357,22 +317,6 @@</span><br><span> smi_set_eos();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void smm_init_completion(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- restore_default_smm_area(default_smm_area);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_lock(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* LOCK the SMM memory window and enable normal SMM.</span><br><span style="color: hsl(0, 100%, 40%);">- * After running this function, only a full reset can</span><br><span style="color: hsl(0, 100%, 40%);">- * make the SMM registers writable again.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Locking SMM.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,</span><br><span style="color: hsl(0, 100%, 40%);">- D_LCK | G_SMRAME | C_BASE_SEG);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void smm_setup_structures(void *gnvs, void *tcg, void *smi1)</span><br><span> {</span><br><span> /* The GDT or coreboot table is going to live here. But a long time</span><br><span>@@ -383,3 +327,15 @@</span><br><span> *(u32 *)0x508 = (u32)smi1;</span><br><span> outb(APM_CNT_GNVS_UPDATE, 0xb2);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_clear_smi_status(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear SMI status */</span><br><span style="color: hsl(120, 100%, 40%);">+ reset_smi_status();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear PM1 status */</span><br><span style="color: hsl(120, 100%, 40%);">+ reset_pm1_status();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set EOS bit so other SMIs can occur. */</span><br><span style="color: hsl(120, 100%, 40%);">+ smi_set_eos();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c</span><br><span>index 7ad00ed..00b6d28 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/smihandler.c</span><br><span>+++ b/src/southbridge/intel/i82801ix/smihandler.c</span><br><span>@@ -222,7 +222,7 @@</span><br><span> outb(reg8, pmbase + SMI_EN);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_smi_apmc(void)</span><br><span> {</span><br><span> u32 pmctrl;</span><br><span> u8 reg8;</span><br><span>@@ -276,7 +276,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_smi_pm1(void)</span><br><span> {</span><br><span> u16 pm1_sts;</span><br><span> volatile u8 cmos_status;</span><br><span>@@ -301,7 +301,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_smi_gpe0(void)</span><br><span> {</span><br><span> u32 gpe0_sts;</span><br><span> </span><br><span>@@ -309,7 +309,7 @@</span><br><span> dump_gpe0_status(gpe0_sts);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_smi_gpi(void)</span><br><span> {</span><br><span> u16 reg16;</span><br><span> reg16 = inw(pmbase + ALT_GP_SMI_STS);</span><br><span>@@ -324,7 +324,7 @@</span><br><span> }</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_smi_tco(void)</span><br><span> {</span><br><span> u32 tco_sts;</span><br><span> </span><br><span>@@ -362,13 +362,13 @@</span><br><span> }</span><br><span> </span><br><span> #if DEBUG_PERIODIC_SMIS</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_smi_periodic(void)</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Periodic SMI.\n");</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_smi_monitor(void)</span><br><span> {</span><br><span> #define IOTRAP(x) (trap_sts & (1 << x))</span><br><span> u32 trap_sts, trap_cycle;</span><br><span>@@ -422,8 +422,7 @@</span><br><span> #undef IOTRAP</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-typedef void (*smi_handler_t)(unsigned int node,</span><br><span style="color: hsl(0, 100%, 40%);">- smm_state_save_area_t *state_save);</span><br><span style="color: hsl(120, 100%, 40%);">+typedef void (*smi_handler_t)(void);</span><br><span> </span><br><span> smi_handler_t southbridge_smi[32] = {</span><br><span> NULL, // [0] reserved</span><br><span>@@ -489,7 +488,7 @@</span><br><span> * @param node</span><br><span> * @param *state_save</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_smi_handler(void)</span><br><span> {</span><br><span> int i, dump = 0;</span><br><span> u32 smi_sts;</span><br><span>@@ -509,7 +508,7 @@</span><br><span> for (i = 0; i < 31; i++) {</span><br><span> if (smi_sts & (1 << i)) {</span><br><span> if (southbridge_smi[i])</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi[i](node, state_save);</span><br><span style="color: hsl(120, 100%, 40%);">+ southbridge_smi[i]();</span><br><span> else {</span><br><span> printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "</span><br><span> "handler available.\n", i);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23419">change 23419</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23419"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 </div>
<div style="display:none"> Gerrit-Change-Number: 23419 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>