[coreboot-gerrit] Change in coreboot[master]: nb/intel/gm45: Allocate a 8M TSEG region

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23418


Change subject: nb/intel/gm45: Allocate a 8M TSEG region
......................................................................

nb/intel/gm45: Allocate a 8M TSEG region

Tested on Thinkpad X200.

Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/ram_calc.c
M src/northbridge/intel/gm45/raminit.c
4 files changed, 32 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/23418/1

diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 34f734c..a71fa89 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -433,6 +433,7 @@
 
 u32 decode_igd_memory_size(u32 gms);
 u32 decode_igd_gtt_size(u32 gsm);
+u32 decode_tseg_size(const u8 esmramc);
 
 void init_iommu(void);
 
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 8215979..2b36c70 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -124,11 +124,16 @@
 
 		/* GTT Graphics Stolen Memory Size (GGMS) */
 		const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
-		printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
+		printk(BIOS_DEBUG, " ,%uM GTT", gsm_sizek >> 10);
 		tomk -= gsm_sizek;
 
 		uma_sizek = gms_sizek + gsm_sizek;
 	}
+	const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
+	const u32 tseg_sizek = decode_tseg_size(esmramc);
+	printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10);
+	tomk -= tseg_sizek;
+	uma_sizek += tseg_sizek;
 
 	printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
 
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 780bed4..d619308 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -64,6 +64,23 @@
 		return 0;
 	}
 }
+/* Decodes TSEG region size to kilobytes. */
+u32 decode_tseg_size(const u8 esmramc)
+{
+	if (!(esmramc & 1))
+		return 0;
+	switch ((esmramc >> 1) & 3) {
+	case 0:
+		return 1 << 10;
+	case 1:
+		return 2 << 10;
+	case 2:
+		return 8 << 10;
+	case 3:
+	default:
+		die("Bad TSEG setting.\n");
+	}
+}
 
 static uintptr_t smm_region_start(void)
 {
@@ -76,12 +93,15 @@
 
 	/* Graphics memory comes next */
 	const u32 ggc = pci_read_config16(dev, D0F0_GGC);
+	const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
 	if (!(ggc & 2)) {
 		/* Graphics memory */
 		tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10;
 		/* GTT Graphics Stolen Memory Size (GGMS) */
 		tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10;
 	}
+	/* TSEG size */
+	tor -= decode_tseg_size(esmramc) << 10;
 	return tor;
 }
 
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index a44e397..b660905 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1242,6 +1242,11 @@
 
 			uma_sizem = (gms_sizek + gsm_sizek) >> 10;
 		}
+		/* TSEG 8M */
+		u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
+		reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
+		pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
+		uma_sizem += 8;
 	}
 
 	const unsigned int mmio_size = get_mmio_size();

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265
Gerrit-Change-Number: 23418
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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