<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23418">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/gm45: Allocate a 8M TSEG region<br><br>Tested on Thinkpad X200.<br><br>Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/gm45/gm45.h<br>M src/northbridge/intel/gm45/northbridge.c<br>M src/northbridge/intel/gm45/ram_calc.c<br>M src/northbridge/intel/gm45/raminit.c<br>4 files changed, 32 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/23418/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h</span><br><span>index 34f734c..a71fa89 100644</span><br><span>--- a/src/northbridge/intel/gm45/gm45.h</span><br><span>+++ b/src/northbridge/intel/gm45/gm45.h</span><br><span>@@ -433,6 +433,7 @@</span><br><span> </span><br><span> u32 decode_igd_memory_size(u32 gms);</span><br><span> u32 decode_igd_gtt_size(u32 gsm);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 decode_tseg_size(const u8 esmramc);</span><br><span> </span><br><span> void init_iommu(void);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c</span><br><span>index 8215979..2b36c70 100644</span><br><span>--- a/src/northbridge/intel/gm45/northbridge.c</span><br><span>+++ b/src/northbridge/intel/gm45/northbridge.c</span><br><span>@@ -124,11 +124,16 @@</span><br><span> </span><br><span> /* GTT Graphics Stolen Memory Size (GGMS) */</span><br><span> const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, " ,%uM GTT", gsm_sizek >> 10);</span><br><span> tomk -= gsm_sizek;</span><br><span> </span><br><span> uma_sizek = gms_sizek + gsm_sizek;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 tseg_sizek = decode_tseg_size(esmramc);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10);</span><br><span style="color: hsl(120, 100%, 40%);">+ tomk -= tseg_sizek;</span><br><span style="color: hsl(120, 100%, 40%);">+ uma_sizek += tseg_sizek;</span><br><span> </span><br><span> printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>index 780bed4..d619308 100644</span><br><span>--- a/src/northbridge/intel/gm45/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>@@ -64,6 +64,23 @@</span><br><span> return 0;</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+/* Decodes TSEG region size to kilobytes. */</span><br><span style="color: hsl(120, 100%, 40%);">+u32 decode_tseg_size(const u8 esmramc)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(esmramc & 1))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ switch ((esmramc >> 1) & 3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1 << 10;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 2 << 10;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 8 << 10;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3:</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Bad TSEG setting.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span> static uintptr_t smm_region_start(void)</span><br><span> {</span><br><span>@@ -76,12 +93,15 @@</span><br><span> </span><br><span> /* Graphics memory comes next */</span><br><span> const u32 ggc = pci_read_config16(dev, D0F0_GGC);</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);</span><br><span> if (!(ggc & 2)) {</span><br><span> /* Graphics memory */</span><br><span> tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10;</span><br><span> /* GTT Graphics Stolen Memory Size (GGMS) */</span><br><span> tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TSEG size */</span><br><span style="color: hsl(120, 100%, 40%);">+ tor -= decode_tseg_size(esmramc) << 10;</span><br><span> return tor;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c</span><br><span>index a44e397..b660905 100644</span><br><span>--- a/src/northbridge/intel/gm45/raminit.c</span><br><span>+++ b/src/northbridge/intel/gm45/raminit.c</span><br><span>@@ -1242,6 +1242,11 @@</span><br><span> </span><br><span> uma_sizem = (gms_sizek + gsm_sizek) >> 10;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TSEG 8M */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ uma_sizem += 8;</span><br><span> }</span><br><span> </span><br><span> const unsigned int mmio_size = get_mmio_size();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23418">change 23418</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23418"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265 </div>
<div style="display:none"> Gerrit-Change-Number: 23418 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>