[coreboot-gerrit] Change in coreboot[master]: src/amd/stoneyridge: Add devicetree ACPI names.

[Justin TerAvest (Code Review)]

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/23417


Change subject: src/amd/stoneyridge: Add devicetree ACPI names.
......................................................................

src/amd/stoneyridge: Add devicetree ACPI names.

This commit adds device name to ACPI name bindings for various entries
in the devicetree.

Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3
Signed-off-by: Justin TerAvest <teravest at chromium.org>
---
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/gpio.c
2 files changed, 37 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/23417/1

diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 3d82c37..d447ffa 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -22,6 +22,7 @@
 #include <device/pci.h>
 #include <soc/cpu.h>
 #include <soc/northbridge.h>
+#include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <amdblocks/psp.h>
 #include <amdblocks/agesawrapper.h>
@@ -35,12 +36,38 @@
 	.acpi_fill_ssdt_generator = generate_cpu_entries,
 };
 
+static const char *soc_acpi_name(const struct device *dev)
+{
+	if (dev->path.type == DEVICE_PATH_DOMAIN)
+		return "PCI0";
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return NULL;
+
+	switch (dev->path.pci.devfn) {
+	case EHCI1_DEVFN:
+		return "EHC0";
+	case LPC_DEVFN:
+		return "LPCB";
+	case SATA_DEVFN:
+		return "STCR";
+	case SD_DEVFN:
+		return "SDCN";
+	case SMBUS_DEVFN:
+		return "SBUS";
+	case XHCI_DEVFN:
+		return "XHC0";
+	default:
+		return NULL;
+	}
+};
+
 struct device_operations pci_domain_ops = {
 	.read_resources	  = domain_read_resources,
 	.set_resources	  = domain_set_resources,
 	.enable_resources = domain_enable_resources,
 	.scan_bus	  = pci_domain_scan_bus,
 	.ops_pci_bus	  = pci_bus_default_ops,
+	.acpi_name	  = soc_acpi_name,
 };
 
 static void enable_dev(device_t dev)
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index 86655fc..62edcd3 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -96,3 +96,13 @@
 	reg |=  GPIO_OUTPUT_ENABLE;
 	write32((void *)(uintptr_t)gpio_num, reg);
 }
+
+const char *gpio_acpi_path(gpio_t gpio)
+{
+	return "\\SB.GPIO";
+}
+
+uint16_t gpio_acpi_pin(gpio_t gpio)
+{
+	return gpio;
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3
Gerrit-Change-Number: 23417
Gerrit-PatchSet: 1
Gerrit-Owner: Justin TerAvest <teravest at chromium.org>
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