<p>Justin TerAvest has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23417">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/amd/stoneyridge: Add devicetree ACPI names.<br><br>This commit adds device name to ACPI name bindings for various entries<br>in the devicetree.<br><br>Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3<br>Signed-off-by: Justin TerAvest <teravest@chromium.org><br>---<br>M src/soc/amd/stoneyridge/chip.c<br>M src/soc/amd/stoneyridge/gpio.c<br>2 files changed, 37 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/23417/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c</span><br><span>index 3d82c37..d447ffa 100644</span><br><span>--- a/src/soc/amd/stoneyridge/chip.c</span><br><span>+++ b/src/soc/amd/stoneyridge/chip.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/northbridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <amdblocks/psp.h></span><br><span> #include <amdblocks/agesawrapper.h></span><br><span>@@ -35,12 +36,38 @@</span><br><span> .acpi_fill_ssdt_generator = generate_cpu_entries,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const char *soc_acpi_name(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type == DEVICE_PATH_DOMAIN)</span><br><span style="color: hsl(120, 100%, 40%);">+ return "PCI0";</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type != DEVICE_PATH_PCI)</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dev->path.pci.devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case EHCI1_DEVFN:</span><br><span style="color: hsl(120, 100%, 40%);">+ return "EHC0";</span><br><span style="color: hsl(120, 100%, 40%);">+ case LPC_DEVFN:</span><br><span style="color: hsl(120, 100%, 40%);">+ return "LPCB";</span><br><span style="color: hsl(120, 100%, 40%);">+ case SATA_DEVFN:</span><br><span style="color: hsl(120, 100%, 40%);">+ return "STCR";</span><br><span style="color: hsl(120, 100%, 40%);">+ case SD_DEVFN:</span><br><span style="color: hsl(120, 100%, 40%);">+ return "SDCN";</span><br><span style="color: hsl(120, 100%, 40%);">+ case SMBUS_DEVFN:</span><br><span style="color: hsl(120, 100%, 40%);">+ return "SBUS";</span><br><span style="color: hsl(120, 100%, 40%);">+ case XHCI_DEVFN:</span><br><span style="color: hsl(120, 100%, 40%);">+ return "XHC0";</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct device_operations pci_domain_ops = {</span><br><span> .read_resources = domain_read_resources,</span><br><span> .set_resources = domain_set_resources,</span><br><span> .enable_resources = domain_enable_resources,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span> .ops_pci_bus = pci_bus_default_ops,</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_name = soc_acpi_name,</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(device_t dev)</span><br><span>diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c</span><br><span>index 86655fc..62edcd3 100644</span><br><span>--- a/src/soc/amd/stoneyridge/gpio.c</span><br><span>+++ b/src/soc/amd/stoneyridge/gpio.c</span><br><span>@@ -96,3 +96,13 @@</span><br><span> reg |= GPIO_OUTPUT_ENABLE;</span><br><span> write32((void *)(uintptr_t)gpio_num, reg);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const char *gpio_acpi_path(gpio_t gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return "\\SB.GPIO";</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint16_t gpio_acpi_pin(gpio_t gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23417">change 23417</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3 </div>
<div style="display:none"> Gerrit-Change-Number: 23417 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Justin TerAvest <teravest@chromium.org> </div>