[coreboot-gerrit] Change in coreboot[master]: cannonlake: enable pch link in bootblock

[Caveh Jalali (Code Review)]

Caveh Jalali has uploaded this change for review. ( https://review.coreboot.org/23401


Change subject: cannonlake: enable pch link in bootblock
......................................................................

cannonlake: enable pch link in bootblock

this moves the call to pch_enable_lpc() from romstage to blootblock.
in other words, it happens earlier in the boot process.  turns out, we
need this to talk to the ec to determine if we're in recovery mode or
not.

BUG=b:69011806
TEST=boots to linux

Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3
Signed-off-by: Caveh Jalali <caveh at google.com>
---
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/romstage/romstage.c
3 files changed, 5 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/23401/1

diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index bfc52ce..d6515f4 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -18,13 +18,13 @@
 bootblock-y += i2c.c
 bootblock-y += memmap.c
 bootblock-y += spi.c
+bootblock-y += lpc.c
 bootblock-$(CONFIG_UART_DEBUG) += uart.c
 
 romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
 romstage-y += gpio.c
 romstage-y += gspi.c
 romstage-y += i2c.c
-romstage-y += lpc.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
 romstage-y += reset.c
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index ae413d5..8e4f7fd 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/pmclib.h>
@@ -174,6 +175,9 @@
 	dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;
 	pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
 	pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
+
+	/* Program generic IO Decode Range */
+	pch_enable_lpc();
 }
 
 void pch_early_init(void)
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 2673f37..8b3794f 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -22,7 +22,6 @@
 #include <console/console.h>
 #include <fsp/util.h>
 #include <intelblocks/cse.h>
-#include <intelblocks/lpc_lib.h>
 #include <intelblocks/pmclib.h>
 #include <memory_info.h>
 #include <soc/iomap.h>
@@ -47,8 +46,6 @@
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);
 
-	/* Program LPC generic decoding */
-	pch_enable_lpc();
 	timestamp_add_now(TS_START_ROMSTAGE);
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3
Gerrit-Change-Number: 23401
Gerrit-PatchSet: 1
Gerrit-Owner: Caveh Jalali <caveh at google.com>
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