<p>Caveh Jalali has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23401">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cannonlake: enable pch link in bootblock<br><br>this moves the call to pch_enable_lpc() from romstage to blootblock.<br>in other words, it happens earlier in the boot process. turns out, we<br>need this to talk to the ec to determine if we're in recovery mode or<br>not.<br><br>BUG=b:69011806<br>TEST=boots to linux<br><br>Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3<br>Signed-off-by: Caveh Jalali <caveh@google.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/bootblock/pch.c<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>3 files changed, 5 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/23401/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index bfc52ce..d6515f4 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -18,13 +18,13 @@</span><br><span> bootblock-y += i2c.c</span><br><span> bootblock-y += memmap.c</span><br><span> bootblock-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += lpc.c</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c</span><br><span> romstage-y += gpio.c</span><br><span> romstage-y += gspi.c</span><br><span> romstage-y += i2c.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += lpc.c</span><br><span> romstage-y += memmap.c</span><br><span> romstage-y += pmutil.c</span><br><span> romstage-y += reset.c</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>index ae413d5..8e4f7fd 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <intelblocks/fast_spi.h></span><br><span> #include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span> #include <intelblocks/pcr.h></span><br><span> #include <intelblocks/rtc.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span>@@ -174,6 +175,9 @@</span><br><span> dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;</span><br><span> pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);</span><br><span> pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program generic IO Decode Range */</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_enable_lpc();</span><br><span> }</span><br><span> </span><br><span> void pch_early_init(void)</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>index 2673f37..8b3794f 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>@@ -22,7 +22,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <fsp/util.h></span><br><span> #include <intelblocks/cse.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/lpc_lib.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <memory_info.h></span><br><span> #include <soc/iomap.h></span><br><span>@@ -47,8 +46,6 @@</span><br><span> /* initialize Heci interface */</span><br><span> heci_init(HECI1_BASE_ADDRESS);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Program LPC generic decoding */</span><br><span style="color: hsl(0, 100%, 40%);">- pch_enable_lpc();</span><br><span> timestamp_add_now(TS_START_ROMSTAGE);</span><br><span> s3wake = pmc_fill_power_state(ps) == ACPI_S3;</span><br><span> fsp_memory_init(s3wake);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23401">change 23401</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23401"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3 </div>
<div style="display:none"> Gerrit-Change-Number: 23401 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Caveh Jalali <caveh@google.com> </div>