[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add Pch iSCLK programming

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23367


Change subject: soc/intel/cannonlake: Add Pch iSCLK programming
......................................................................

soc/intel/cannonlake: Add Pch iSCLK programming

In order to reduce BOM cost and board area for imaging solution, the sensor
requires a 19.2/24MHz reference clock from PCH. In addition to that, having
PCH to supply the sensor reference clock will prevent dependency on CPU power
management and also avoid level shifter cost.

Pch iSCLK is only required for CNP-LP with the camera sensor on the platform.

BUG=None
TEST=Boot up into OS and read back PCH iSCLK programming through iotools.

Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/cannonlake/include/soc/pcr_ids.h
3 files changed, 39 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/23367/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 50ae8ba..018b1f3 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -257,6 +257,9 @@
 
 	/* I2C bus configuration */
 	struct dw_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX];
+
+	/* Pch iSCLK */
+	uint8_t PchiSCLK;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 8aa7c04..23f1d79 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -37,6 +37,12 @@
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS	(1 << 8)
 
+#define CAMERA1_CAMERA		0x8000
+#define CAMERA2_CAMERA		0x8080
+#define CAM_CLK_EN		(1 << 1)
+#define MIPI_CLK		(1 << 0)
+#define HDPLL_CLK		(0 << 0)
+
 static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
 {
 	uint32_t reg32;
@@ -63,6 +69,31 @@
 	pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));
 }
 
+static void pch_enable_iSCLK(void)
+{
+	device_t dev = PCH_DEV_P2SB;
+
+	/*
+	 * if p2sb device 1f.1 is not present or hidden in devicetree
+	 * p2sb device becomes NULL
+	 */
+	if (!dev)
+		return;
+
+	/* unhide p2sb device */
+	pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);
+
+	/* enable pch iSCLK */
+	pcr_or32(PID_ISCLK, CAMERA1_CAMERA, CAM_CLK_EN | MIPI_CLK);
+	pcr_or32(PID_ISCLK, CAMERA2_CAMERA, CAM_CLK_EN | MIPI_CLK);
+
+	disable_sideband_access();
+
+	/* hide p2sb device */
+	pci_write_config8(dev, PCH_P2SB_E0 + 1, 1);
+}
+
+
 static void pch_disable_heci(void)
 {
 	device_t dev = PCH_DEV_P2SB;
@@ -127,6 +158,10 @@
 	/* we should disable Heci1 based on the devicetree policy */
 	if (config->HeciEnabled == 0)
 		pch_disable_heci();
+
+	/* Enable Pch iSCLK before OS boot */
+	if (config->PchiSCLK == 1)
+		pch_enable_iSCLK();
 }
 
 static void soc_finalize(void *unused)
diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
index 65576aa..b77eab8 100644
--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
@@ -25,6 +25,7 @@
 #define PID_GPIOCOM0	0x6e
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
+#define PID_ISCLK	0xad
 #define PID_PSF1	0xba
 #define PID_PSF2	0xbb
 #define PID_PSF3	0xbc

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6
Gerrit-Change-Number: 23367
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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