[coreboot-gerrit] Change in coreboot[master]: nb/intel/i945: Use ESMRAMC of 0x9e

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23330


Change subject: nb/intel/i945: Use ESMRAMC of 0x9e
......................................................................

nb/intel/i945: Use ESMRAMC of 0x9e

Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/i945/ram_calc.c
3 files changed, 3 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/23330/1

diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 330ace1..5929a1d 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -75,7 +75,7 @@
 #define LAC		0x97	/* Legacy Access Control */
 #define TOLUD		0x9c	/* Top of Low Used Memory */
 #define SMRAM		0x9d	/* System Management RAM Control */
-#define ESMRAM		0x9e	/* Extended System Management RAM Control */
+#define ESMRAMC		0x9e	/* Extended System Management RAM Control */
 
 #define TOM		0xa0
 
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 57f4388..fdb37b1 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -95,7 +95,7 @@
 		uma_memory_size = uma_size * 1024ULL;
 	}
 
-	reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
+	reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), ESMRAMC);
 	if (reg8 & 1) {
 		int tseg_size = 0;
 		printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 0c337bb..990df97 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -36,7 +36,7 @@
 		tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;
 
 	/* if TSEG enabled subtract size */
-	switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
+	switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC) & 0x07) {
 	case 0x01:
 		/* 1MB TSEG */
 		tom -= 0x100000;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71
Gerrit-Change-Number: 23330
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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