<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23330">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/i945: Use ESMRAMC of 0x9e<br><br>Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/intel/i945/i945.h<br>M src/northbridge/intel/i945/northbridge.c<br>M src/northbridge/intel/i945/ram_calc.c<br>3 files changed, 3 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/23330/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h</span><br><span>index 330ace1..5929a1d 100644</span><br><span>--- a/src/northbridge/intel/i945/i945.h</span><br><span>+++ b/src/northbridge/intel/i945/i945.h</span><br><span>@@ -75,7 +75,7 @@</span><br><span> #define LAC 0x97 /* Legacy Access Control */</span><br><span> #define TOLUD 0x9c /* Top of Low Used Memory */</span><br><span> #define SMRAM 0x9d /* System Management RAM Control */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ESMRAM 0x9e /* Extended System Management RAM Control */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ESMRAMC 0x9e /* Extended System Management RAM Control */</span><br><span> </span><br><span> #define TOM 0xa0</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c</span><br><span>index 57f4388..fdb37b1 100644</span><br><span>--- a/src/northbridge/intel/i945/northbridge.c</span><br><span>+++ b/src/northbridge/intel/i945/northbridge.c</span><br><span>@@ -95,7 +95,7 @@</span><br><span> uma_memory_size = uma_size * 1024ULL;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), ESMRAMC);</span><br><span> if (reg8 & 1) {</span><br><span> int tseg_size = 0;</span><br><span> printk(BIOS_DEBUG, "TSEG decoded, subtracting ");</span><br><span>diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c</span><br><span>index 0c337bb..990df97 100644</span><br><span>--- a/src/northbridge/intel/i945/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/i945/ram_calc.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;</span><br><span> </span><br><span> /* if TSEG enabled subtract size */</span><br><span style="color: hsl(0, 100%, 40%);">- switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC) & 0x07) {</span><br><span> case 0x01:</span><br><span> /* 1MB TSEG */</span><br><span> tom -= 0x100000;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23330">change 23330</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23330"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71 </div>
<div style="display:none"> Gerrit-Change-Number: 23330 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>