[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6: Move RCBA macros to a common location
Arthur Heymans (Code Review)
gerrit at coreboot.org
Tue Jan 16 14:27:51 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23287
Change subject: sb/intel/bd82x6: Move RCBA macros to a common location
......................................................................
sb/intel/bd82x6: Move RCBA macros to a common location
Many generations of Intel hardware have identical code concerning the
RCBA.
Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/model_206ax/bootblock.c
M src/mainboard/asrock/b75pro3-m/mainboard.c
M src/mainboard/asrock/b75pro3-m/romstage.c
M src/mainboard/compulab/intense_pc/mainboard.c
M src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
M src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
M src/mainboard/google/beltino/lan.c
M src/mainboard/google/butterfly/acpi_tables.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/butterfly/mainboard.c
M src/mainboard/google/butterfly/mainboard_smi.c
M src/mainboard/google/link/acpi_tables.c
M src/mainboard/google/link/chromeos.c
M src/mainboard/google/link/i915.c
M src/mainboard/google/link/mainboard.c
M src/mainboard/google/link/mainboard_smi.c
M src/mainboard/google/parrot/acpi_tables.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/parrot/mainboard.c
M src/mainboard/google/parrot/smihandler.c
M src/mainboard/google/stout/acpi_tables.c
M src/mainboard/google/stout/chromeos.c
M src/mainboard/google/stout/ec.c
M src/mainboard/google/stout/mainboard.c
M src/mainboard/google/stout/mainboard_smi.c
M src/mainboard/intel/emeraldlake2/chromeos.c
M src/mainboard/intel/emeraldlake2/mainboard.c
M src/mainboard/intel/emeraldlake2/smihandler.c
M src/mainboard/kontron/ktqm77/acpi_tables.c
M src/mainboard/kontron/ktqm77/mainboard.c
M src/mainboard/lenovo/l520/acpi_tables.c
M src/mainboard/lenovo/l520/smihandler.c
M src/mainboard/lenovo/s230u/smihandler.c
M src/mainboard/lenovo/t420/smihandler.c
M src/mainboard/lenovo/t420s/acpi_tables.c
M src/mainboard/lenovo/t420s/smihandler.c
M src/mainboard/lenovo/t430/smihandler.c
M src/mainboard/lenovo/t430s/smihandler.c
M src/mainboard/lenovo/t520/acpi_tables.c
M src/mainboard/lenovo/t520/smihandler.c
M src/mainboard/lenovo/t530/acpi_tables.c
M src/mainboard/lenovo/t530/smihandler.c
M src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/smihandler.c
M src/mainboard/lenovo/x220/acpi_tables.c
M src/mainboard/lenovo/x220/smihandler.c
M src/mainboard/lenovo/x230/acpi_tables.c
M src/mainboard/lenovo/x230/smihandler.c
M src/mainboard/samsung/lumpy/chromeos.c
M src/mainboard/samsung/lumpy/mainboard.c
M src/mainboard/samsung/lumpy/smihandler.c
M src/mainboard/samsung/stumpy/chromeos.c
M src/mainboard/samsung/stumpy/mainboard.c
M src/mainboard/samsung/stumpy/smihandler.c
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/sandybridge.h
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/bootblock.c
M src/southbridge/intel/bd82x6x/early_pch.c
M src/southbridge/intel/bd82x6x/early_rcba.c
M src/southbridge/intel/bd82x6x/early_spi.c
M src/southbridge/intel/bd82x6x/early_thermal.c
M src/southbridge/intel/bd82x6x/finalize.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/smihandler.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
A src/southbridge/intel/common/rcba.h
73 files changed, 290 insertions(+), 149 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/23287/1
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 670b097..90215a4 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -28,6 +28,7 @@
IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#else
#error "CPU must be paired with Intel BD82X6X or C216 southbridge"
#endif
diff --git a/src/mainboard/asrock/b75pro3-m/mainboard.c b/src/mainboard/asrock/b75pro3-m/mainboard.c
index f0d0cf7..76dea4e 100644
--- a/src/mainboard/asrock/b75pro3-m/mainboard.c
+++ b/src/mainboard/asrock/b75pro3-m/mainboard.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
static void mainboard_enable(device_t dev)
{
diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c
index f556443..bde1cb4 100644
--- a/src/mainboard/asrock/b75pro3-m/romstage.c
+++ b/src/mainboard/asrock/b75pro3-m/romstage.c
@@ -15,6 +15,7 @@
*/
#include "northbridge/intel/sandybridge/raminit_native.h"
+#include <southbridge/intel/common/rcba.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#include <superio/nuvoton/common/nuvoton.h>
diff --git a/src/mainboard/compulab/intense_pc/mainboard.c b/src/mainboard/compulab/intense_pc/mainboard.c
index f06e900..d1c5d6a 100644
--- a/src/mainboard/compulab/intense_pc/mainboard.c
+++ b/src/mainboard/compulab/intense_pc/mainboard.c
@@ -16,6 +16,7 @@
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <ec/acpi/ec.h>
#include <console/console.h>
#include <pc80/keyboard.h>
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
index bbf3241..d33dfc5 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
@@ -26,6 +26,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
index bbf3241..d33dfc5 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
@@ -26,6 +26,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c
index 140c814..940b4de 100644
--- a/src/mainboard/google/beltino/lan.c
+++ b/src/mainboard/google/beltino/lan.c
@@ -22,6 +22,7 @@
#include <device/pci.h>
#include <fmap.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include "onboard.h"
static unsigned int search(char *p, u8 *a, unsigned int lengthp,
diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c
index e132232..3c867e3 100644
--- a/src/mainboard/google/butterfly/acpi_tables.c
+++ b/src/mainboard/google/butterfly/acpi_tables.c
@@ -28,6 +28,7 @@
#include <ec/quanta/ene_kb3940q/ec.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index 42f6189..f3bd518 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <ec/quanta/ene_kb3940q/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index a100981..3b2a460 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -31,6 +31,7 @@
#include "onboard.h"
#include "ec.h"
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <smbios.h>
#include <device/pci.h>
#include <ec/quanta/ene_kb3940q/ec.h>
diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c
index 03e0316..8c64b10 100644
--- a/src/mainboard/google/butterfly/mainboard_smi.c
+++ b/src/mainboard/google/butterfly/mainboard_smi.c
@@ -18,6 +18,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
index 28d9922..3e7787e 100644
--- a/src/mainboard/google/link/acpi_tables.c
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -29,6 +29,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
index 335f1f7..3cb7e1f 100644
--- a/src/mainboard/google/link/chromeos.c
+++ b/src/mainboard/google/link/chromeos.c
@@ -16,6 +16,7 @@
#include <string.h>
#include <bootmode.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index 9ab3149..c1f834a 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -30,6 +30,7 @@
#include "onboard.h"
#include "ec.h"
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <northbridge/intel/sandybridge/gma.h>
#include <smbios.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index 24062e9..a2affcd 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -32,6 +32,7 @@
#include "onboard.h"
#include "ec.h"
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <smbios.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c
index 0babb54..28c5cee 100644
--- a/src/mainboard/google/link/mainboard_smi.c
+++ b/src/mainboard/google/link/mainboard_smi.c
@@ -19,6 +19,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
index ae36ba0..e102d7c 100644
--- a/src/mainboard/google/parrot/acpi_tables.c
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -29,6 +29,7 @@
#include "ec.h"
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
#include "onboard.h"
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index d2448eb..195b118 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <ec/compal/ene932/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c
index 4d357f8..9baac21 100644
--- a/src/mainboard/google/parrot/mainboard.c
+++ b/src/mainboard/google/parrot/mainboard.c
@@ -29,6 +29,7 @@
#include "onboard.h"
#include "ec.h"
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <smbios.h>
#include <device/pci.h>
#include <ec/compal/ene932/ec.h>
diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c
index 176e33c..3dab9c9 100644
--- a/src/mainboard/google/parrot/smihandler.c
+++ b/src/mainboard/google/parrot/smihandler.c
@@ -18,6 +18,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index 078cba2..72002a0 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -31,6 +31,7 @@
#include "onboard.h"
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index 047e6a1..75255fe 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c
index a459d0c..466e8be 100644
--- a/src/mainboard/google/stout/ec.c
+++ b/src/mainboard/google/stout/ec.c
@@ -22,6 +22,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <elog.h>
#include "ec.h"
diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c
index 4e3839f..4a4838a 100644
--- a/src/mainboard/google/stout/mainboard.c
+++ b/src/mainboard/google/stout/mainboard.c
@@ -29,6 +29,7 @@
#include "onboard.h"
#include "ec.h"
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <smbios.h>
#include <device/pci.h>
#include <ec/quanta/it8518/ec.h>
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c
index e25c576..9f368e1 100644
--- a/src/mainboard/google/stout/mainboard_smi.c
+++ b/src/mainboard/google/stout/mainboard_smi.c
@@ -18,6 +18,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index eac995a..614c7f4 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c
index 654b1de..cdcde3d 100644
--- a/src/mainboard/intel/emeraldlake2/mainboard.c
+++ b/src/mainboard/intel/emeraldlake2/mainboard.c
@@ -28,6 +28,7 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <vendorcode/google/chromeos/chromeos.h>
// mainboard_enable is executed as first thing after
diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c
index 3662e6e..3cf2361 100644
--- a/src/mainboard/intel/emeraldlake2/smihandler.c
+++ b/src/mainboard/intel/emeraldlake2/smihandler.c
@@ -19,6 +19,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c
index 312557c..c8b0006 100644
--- a/src/mainboard/kontron/ktqm77/acpi_tables.c
+++ b/src/mainboard/kontron/ktqm77/acpi_tables.c
@@ -26,6 +26,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c
index 5a697f0..985a49d 100644
--- a/src/mainboard/kontron/ktqm77/mainboard.c
+++ b/src/mainboard/kontron/ktqm77/mainboard.c
@@ -30,6 +30,7 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
static int int15_handler(void)
diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c
index 9ce40fb..a1191f3 100644
--- a/src/mainboard/lenovo/l520/acpi_tables.c
+++ b/src/mainboard/lenovo/l520/acpi_tables.c
@@ -16,6 +16,7 @@
*/
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c
index f0c7a04..831ddd5 100644
--- a/src/mainboard/lenovo/l520/smihandler.c
+++ b/src/mainboard/lenovo/l520/smihandler.c
@@ -21,6 +21,7 @@
#include <ec/acpi/ec.h>
#include <ec/lenovo/h8/h8.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#define GPE_EC_SCI 6
/* FIXME: check this */
diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c
index 755f176..3be54f9 100644
--- a/src/mainboard/lenovo/s230u/smihandler.c
+++ b/src/mainboard/lenovo/s230u/smihandler.c
@@ -25,6 +25,7 @@
#include <ec/acpi/ec.h>
#include <ec/compal/ene932/ec.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#define GPE_PALMDET1 2
#define GPE_PALMDET2 4
diff --git a/src/mainboard/lenovo/t420/smihandler.c b/src/mainboard/lenovo/t420/smihandler.c
index 825a20b..93a7115 100644
--- a/src/mainboard/lenovo/t420/smihandler.c
+++ b/src/mainboard/lenovo/t420/smihandler.c
@@ -21,6 +21,7 @@
#include <ec/acpi/ec.h>
#include <ec/lenovo/h8/h8.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c
index 1a6cb83..7b05945 100644
--- a/src/mainboard/lenovo/t420s/acpi_tables.c
+++ b/src/mainboard/lenovo/t420s/acpi_tables.c
@@ -26,6 +26,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c
index 471095e..f198a81 100644
--- a/src/mainboard/lenovo/t420s/smihandler.c
+++ b/src/mainboard/lenovo/t420s/smihandler.c
@@ -24,6 +24,7 @@
#include <delay.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c
index 7af9e7d..d38d60e 100644
--- a/src/mainboard/lenovo/t430/smihandler.c
+++ b/src/mainboard/lenovo/t430/smihandler.c
@@ -22,6 +22,7 @@
#include <ec/lenovo/h8/h8.h>
#include <delay.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c
index 512e631..786827c 100644
--- a/src/mainboard/lenovo/t430s/smihandler.c
+++ b/src/mainboard/lenovo/t430s/smihandler.c
@@ -22,6 +22,7 @@
#include <ec/lenovo/h8/h8.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c
index b1c4733..7e8d436 100644
--- a/src/mainboard/lenovo/t520/acpi_tables.c
+++ b/src/mainboard/lenovo/t520/acpi_tables.c
@@ -26,6 +26,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c
index 3fa8e30..371482d 100644
--- a/src/mainboard/lenovo/t520/smihandler.c
+++ b/src/mainboard/lenovo/t520/smihandler.c
@@ -24,6 +24,7 @@
#include <delay.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c
index b1c4733..7e8d436 100644
--- a/src/mainboard/lenovo/t530/acpi_tables.c
+++ b/src/mainboard/lenovo/t530/acpi_tables.c
@@ -26,6 +26,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c
index 1dfd87e..bf94b10 100644
--- a/src/mainboard/lenovo/t530/smihandler.c
+++ b/src/mainboard/lenovo/t530/smihandler.c
@@ -24,6 +24,7 @@
#include <delay.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
index 2c148d4..889290d 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
@@ -28,6 +28,7 @@
#include <cpu/x86/msr.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index 5f7b82e..48bf6a5 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -32,6 +32,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c
index 09dcbf2..0b87f06 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c
@@ -21,6 +21,7 @@
#include <ec/acpi/ec.h>
#include <ec/lenovo/h8/h8.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c
index c9e9407..7245529 100644
--- a/src/mainboard/lenovo/x220/acpi_tables.c
+++ b/src/mainboard/lenovo/x220/acpi_tables.c
@@ -26,6 +26,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c
index 1dfd87e..bf94b10 100644
--- a/src/mainboard/lenovo/x220/smihandler.c
+++ b/src/mainboard/lenovo/x220/smihandler.c
@@ -24,6 +24,7 @@
#include <delay.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c
index c9e9407..7245529 100644
--- a/src/mainboard/lenovo/x230/acpi_tables.c
+++ b/src/mainboard/lenovo/x230/acpi_tables.c
@@ -26,6 +26,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c
index 4572cae..62700d9 100644
--- a/src/mainboard/lenovo/x230/smihandler.c
+++ b/src/mainboard/lenovo/x230/smihandler.c
@@ -21,6 +21,7 @@
#include <ec/acpi/ec.h>
#include <ec/lenovo/h8/h8.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index a287c74..b1e0b2e 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c
index 3de067e..5f6bd8a 100644
--- a/src/mainboard/samsung/lumpy/mainboard.c
+++ b/src/mainboard/samsung/lumpy/mainboard.c
@@ -30,6 +30,7 @@
#include "ec.h"
#include "onboard.h"
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <smbios.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c
index 9690aee..7df6b07 100644
--- a/src/mainboard/samsung/lumpy/smihandler.c
+++ b/src/mainboard/samsung/lumpy/smihandler.c
@@ -18,6 +18,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index 01d81d7..c67fd9a 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c
index 654b1de..cdcde3d 100644
--- a/src/mainboard/samsung/stumpy/mainboard.c
+++ b/src/mainboard/samsung/stumpy/mainboard.c
@@ -28,6 +28,7 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <vendorcode/google/chromeos/chromeos.h>
// mainboard_enable is executed as first thing after
diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c
index 00148f2..2240d69 100644
--- a/src/mainboard/samsung/stumpy/smihandler.c
+++ b/src/mainboard/samsung/stumpy/smihandler.c
@@ -19,6 +19,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 2f1b790..612e25b 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -24,6 +24,7 @@
#include <cbmem.h>
#include <pc80/mc146818rtc.h>
#include <romstage_handoff.h>
+#include <southbridge/intel/common/rcba.h>
#include "sandybridge.h"
static void sandybridge_setup_bars(void)
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index dd1a58c..2f844bc 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -58,6 +58,7 @@
#define IOMMU_BASE2 0xfed91000ULL
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 9c8eaf6..02165d6 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -23,6 +23,7 @@
#include <arch/io.h>
#include <delay.h>
#include <device/azalia_device.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#define HDA_ICII_REG 0x68
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 8541903..b3a1911 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -15,6 +15,7 @@
#include <arch/io.h>
#include <cpu/x86/tsc.h>
+#include "southbridge/intel/common/rcba.h"
#include "pch.h"
static void store_initial_timestamp(void)
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 4015495..427e58c 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -24,6 +24,7 @@
#include <device/pci_def.h>
#include <delay.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
/* For DMI bar. */
#include "northbridge/intel/sandybridge/sandybridge.h"
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index eeecb5f..190a7c1 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include "pch.h"
+#include <southbridge/intel/common/rcba.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
void
diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c
index 1400837..a9ecd82 100644
--- a/src/southbridge/intel/bd82x6x/early_spi.c
+++ b/src/southbridge/intel/bd82x6x/early_spi.c
@@ -19,6 +19,7 @@
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <delay.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#define SPI_DELAY 10 /* 10us */
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index a5c63b6..37df501 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -16,6 +16,7 @@
#include <arch/io.h>
#include "pch.h"
+#include <southbridge/intel/common/rcba.h>
#include "cpu/intel/model_206ax/model_206ax.h"
#include <cpu/x86/msr.h>
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index fe28af0..6b38fcd 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -17,6 +17,7 @@
#include <arch/io.h>
#include <console/post_codes.h>
#include <cpu/x86/smm.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include <spi-generic.h>
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 7f61669..4212d1a 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -32,6 +32,7 @@
#include <cbmem.h>
#include <string.h>
#include <cpu/x86/smm.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 70ba301..a5c5e52 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -39,6 +39,7 @@
# include <device/pci.h>
#endif
+#include <southbridge/intel/common/rcba.h>
#include "me.h"
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 2e29233..6463f96 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -39,6 +39,7 @@
# include <device/pci.h>
#endif
+#include <southbridge/intel/common/rcba.h>
#include "me.h"
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 0b0fc35..73c84bb 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -24,6 +24,7 @@
#include <device/device.h>
#include <device/pci.h>
#endif
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include <string.h>
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 83d9d8d..78ceb22 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -45,12 +45,6 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
-#ifndef __ACPI__
-#define DEFAULT_RCBA ((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA 0xfed1c000
-#endif
-
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)
#define CROS_GPIO_DEVICE_NAME "CougarPoint"
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
@@ -277,73 +271,6 @@
/* Root Complex Register Block */
#define RCBA 0xf0
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
-#define RCBA_AND_OR(bits, x, and, or) \
- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
-
-#define VCH 0x0000 /* 32bit */
-#define VCAP1 0x0004 /* 32bit */
-#define VCAP2 0x0008 /* 32bit */
-#define PVC 0x000c /* 16bit */
-#define PVS 0x000e /* 16bit */
-
-#define V0CAP 0x0010 /* 32bit */
-#define V0CTL 0x0014 /* 32bit */
-#define V0STS 0x001a /* 16bit */
-
-#define V1CAP 0x001c /* 32bit */
-#define V1CTL 0x0020 /* 32bit */
-#define V1STS 0x0026 /* 16bit */
-
-#define RCTCL 0x0100 /* 32bit */
-#define ESD 0x0104 /* 32bit */
-#define ULD 0x0110 /* 32bit */
-#define ULBA 0x0118 /* 64bit */
-
-#define RP1D 0x0120 /* 32bit */
-#define RP1BA 0x0128 /* 64bit */
-#define RP2D 0x0130 /* 32bit */
-#define RP2BA 0x0138 /* 64bit */
-#define RP3D 0x0140 /* 32bit */
-#define RP3BA 0x0148 /* 64bit */
-#define RP4D 0x0150 /* 32bit */
-#define RP4BA 0x0158 /* 64bit */
-#define HDD 0x0160 /* 32bit */
-#define HDBA 0x0168 /* 64bit */
-#define RP5D 0x0170 /* 32bit */
-#define RP5BA 0x0178 /* 64bit */
-#define RP6D 0x0180 /* 32bit */
-#define RP6BA 0x0188 /* 64bit */
-
-#define RPC 0x0400 /* 32bit */
-#define RPFN 0x0404 /* 32bit */
-
-/* Root Port configuratinon space hide */
-#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
-/* Get the function number assigned to a Root Port */
-#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
-/* Set the function number for a Root Port */
-#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
-/* Root Port function number mask */
-#define RPFN_FNMASK(port) (7 << ((port) * 4))
-
-#define TRSR 0x1e00 /* 8bit */
-#define TRCR 0x1e10 /* 64bit */
-#define TWDR 0x1e18 /* 64bit */
-
-#define IOTR0 0x1e80 /* 64bit */
-#define IOTR1 0x1e88 /* 64bit */
-#define IOTR2 0x1e90 /* 64bit */
-#define IOTR3 0x1e98 /* 64bit */
-
-#define TCTL 0x3000 /* 8bit */
#define NOINT 0
#define INTA 1
@@ -373,85 +300,9 @@
#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
-#define D31IP 0x3100 /* 32bit */
-#define D31IP_TTIP 24 /* Thermal Throttle Pin */
-#define D31IP_SIP2 20 /* SATA Pin 2 */
-#define D31IP_SMIP 12 /* SMBUS Pin */
-#define D31IP_SIP 8 /* SATA Pin */
-#define D30IP 0x3104 /* 32bit */
-#define D30IP_PIP 0 /* PCI Bridge Pin */
-#define D29IP 0x3108 /* 32bit */
-#define D29IP_E1P 0 /* EHCI #1 Pin */
-#define D28IP 0x310c /* 32bit */
-#define D28IP_P8IP 28 /* PCI Express Port 8 */
-#define D28IP_P7IP 24 /* PCI Express Port 7 */
-#define D28IP_P6IP 20 /* PCI Express Port 6 */
-#define D28IP_P5IP 16 /* PCI Express Port 5 */
-#define D28IP_P4IP 12 /* PCI Express Port 4 */
-#define D28IP_P3IP 8 /* PCI Express Port 3 */
-#define D28IP_P2IP 4 /* PCI Express Port 2 */
-#define D28IP_P1IP 0 /* PCI Express Port 1 */
-#define D27IP 0x3110 /* 32bit */
-#define D27IP_ZIP 0 /* HD Audio Pin */
-#define D26IP 0x3114 /* 32bit */
-#define D26IP_E2P 0 /* EHCI #2 Pin */
-#define D25IP 0x3118 /* 32bit */
-#define D25IP_LIP 0 /* GbE LAN Pin */
-#define D22IP 0x3124 /* 32bit */
-#define D22IP_KTIP 12 /* KT Pin */
-#define D22IP_IDERIP 8 /* IDE-R Pin */
-#define D22IP_MEI2IP 4 /* MEI #2 Pin */
-#define D22IP_MEI1IP 0 /* MEI #1 Pin */
-#define D20IP 0x3128 /* 32bit */
-#define D20IP_XHCIIP 0
-#define D31IR 0x3140 /* 16bit */
-#define D30IR 0x3142 /* 16bit */
-#define D29IR 0x3144 /* 16bit */
-#define D28IR 0x3146 /* 16bit */
-#define D27IR 0x3148 /* 16bit */
-#define D26IR 0x314c /* 16bit */
-#define D25IR 0x3150 /* 16bit */
-#define D22IR 0x315c /* 16bit */
-#define D20IR 0x3160 /* 16bit */
-#define OIC 0x31fe /* 16bit */
#define SOFT_RESET_CTRL 0x38f4
#define SOFT_RESET_DATA 0x38f8
-#define DIR_ROUTE(x,a,b,c,d) \
- RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
- ((b) << DIR_IBR) | ((a) << DIR_IAR))
-
-#define RC 0x3400 /* 32bit */
-#define HPTC 0x3404 /* 32bit */
-#define GCS 0x3410 /* 32bit */
-#define BUC 0x3414 /* 32bit */
-#define PCH_DISABLE_GBE (1 << 5)
-#define FD 0x3418 /* 32bit */
-#define DISPBDF 0x3424 /* 16bit */
-#define FD2 0x3428 /* 32bit */
-#define CG 0x341c /* 32bit */
-
-/* Function Disable 1 RCBA 0x3418 */
-#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
-#define PCH_DISABLE_P2P (1 << 1)
-#define PCH_DISABLE_SATA1 (1 << 2)
-#define PCH_DISABLE_SMBUS (1 << 3)
-#define PCH_DISABLE_HD_AUDIO (1 << 4)
-#define PCH_DISABLE_EHCI2 (1 << 13)
-#define PCH_DISABLE_LPC (1 << 14)
-#define PCH_DISABLE_EHCI1 (1 << 15)
-#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
-#define PCH_DISABLE_THERMAL (1 << 24)
-#define PCH_DISABLE_SATA2 (1 << 25)
-#define PCH_DISABLE_XHCI (1 << 27)
-
-/* Function Disable 2 RCBA 0x3428 */
-#define PCH_DISABLE_KT (1 << 4)
-#define PCH_DISABLE_IDER (1 << 3)
-#define PCH_DISABLE_MEI2 (1 << 2)
-#define PCH_DISABLE_MEI1 (1 << 1)
-#define PCH_ENABLE_DBDF (1 << 0)
-
/* USB Port Disable Override */
#define USBPDO 0x359c /* 32bit */
/* USB Overcurrent MAP Register */
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 34b7694..1f4c157 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -21,6 +21,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/common/pciehp.h>
#include <assert.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
static void pch_pcie_pm_early(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 165acab..bf72b5e 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -23,6 +23,7 @@
#include <elog.h>
#include <halt.h>
#include <pc80/mc146818rtc.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include "nvs.h"
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 90b29c4..b5ce820 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include <device/pci_ehci.h>
#include <arch/io.h>
diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h
new file mode 100644
index 0000000..1399fde
--- /dev/null
+++ b/src/southbridge/intel/common/rcba.h
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
+#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
+
+/*
+ * The DnnIR registers use common RCBA offsets across these chipsets:
+ * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint
+ *
+ * However not all registers are in use on all of these.
+ */
+
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
+#define DEFAULT_RCBA 0xfed1c000
+#endif
+
+#ifndef __ACPI__
+
+#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))
+#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))
+#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))
+
+#define RCBA_AND_OR(bits, x, and, or) \
+ (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))
+#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
+
+
+#define VCH 0x0000 /* 32bit */
+#define VCAP1 0x0004 /* 32bit */
+#define VCAP2 0x0008 /* 32bit */
+#define PVC 0x000c /* 16bit */
+#define PVS 0x000e /* 16bit */
+
+#define V0CAP 0x0010 /* 32bit */
+#define V0CTL 0x0014 /* 32bit */
+#define V0STS 0x001a /* 16bit */
+
+#define V1CAP 0x001c /* 32bit */
+#define V1CTL 0x0020 /* 32bit */
+#define V1STS 0x0026 /* 16bit */
+
+#define RCTCL 0x0100 /* 32bit */
+#define ESD 0x0104 /* 32bit */
+#define ULD 0x0110 /* 32bit */
+#define ULBA 0x0118 /* 64bit */
+
+#define RP1D 0x0120 /* 32bit */
+#define RP1BA 0x0128 /* 64bit */
+#define RP2D 0x0130 /* 32bit */
+#define RP2BA 0x0138 /* 64bit */
+#define RP3D 0x0140 /* 32bit */
+#define RP3BA 0x0148 /* 64bit */
+#define RP4D 0x0150 /* 32bit */
+#define RP4BA 0x0158 /* 64bit */
+#define HDD 0x0160 /* 32bit */
+#define HDBA 0x0168 /* 64bit */
+#define RP5D 0x0170 /* 32bit */
+#define RP5BA 0x0178 /* 64bit */
+#define RP6D 0x0180 /* 32bit */
+#define RP6BA 0x0188 /* 64bit */
+
+#define RPC 0x0400 /* 32bit */
+#define RPFN 0x0404 /* 32bit */
+
+/* Root Port configuratinon space hide */
+#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
+/* Get the function number assigned to a Root Port */
+#define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7)
+/* Set the function number for a Root Port */
+#define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4))
+/* Root Port function number mask */
+#define RPFN_FNMASK(port) (7 << ((port) * 4))
+
+#define TRSR 0x1e00 /* 8bit */
+#define TRCR 0x1e10 /* 64bit */
+#define TWDR 0x1e18 /* 64bit */
+
+#define IOTR0 0x1e80 /* 64bit */
+#define IOTR1 0x1e88 /* 64bit */
+#define IOTR2 0x1e90 /* 64bit */
+#define IOTR3 0x1e98 /* 64bit */
+
+#define TCTL 0x3000 /* 8bit */
+
+
+#define D31IP 0x3100 /* 32bit */
+#define D31IP_TTIP 24 /* Thermal Throttle Pin */
+#define D31IP_SIP2 20 /* SATA Pin 2 */
+#define D31IP_SMIP 12 /* SMBUS Pin */
+#define D31IP_SIP 8 /* SATA Pin */
+#define D30IP 0x3104 /* 32bit */
+#define D30IP_PIP 0 /* PCI Bridge Pin */
+#define D29IP 0x3108 /* 32bit */
+#define D29IP_E1P 0 /* EHCI #1 Pin */
+#define D28IP 0x310c /* 32bit */
+#define D28IP_P8IP 28 /* PCI Express Port 8 */
+#define D28IP_P7IP 24 /* PCI Express Port 7 */
+#define D28IP_P6IP 20 /* PCI Express Port 6 */
+#define D28IP_P5IP 16 /* PCI Express Port 5 */
+#define D28IP_P4IP 12 /* PCI Express Port 4 */
+#define D28IP_P3IP 8 /* PCI Express Port 3 */
+#define D28IP_P2IP 4 /* PCI Express Port 2 */
+#define D28IP_P1IP 0 /* PCI Express Port 1 */
+#define D27IP 0x3110 /* 32bit */
+#define D27IP_ZIP 0 /* HD Audio Pin */
+#define D26IP 0x3114 /* 32bit */
+#define D26IP_E2P 0 /* EHCI #2 Pin */
+#define D25IP 0x3118 /* 32bit */
+#define D25IP_LIP 0 /* GbE LAN Pin */
+#define D22IP 0x3124 /* 32bit */
+#define D22IP_KTIP 12 /* KT Pin */
+#define D22IP_IDERIP 8 /* IDE-R Pin */
+#define D22IP_MEI2IP 4 /* MEI #2 Pin */
+#define D22IP_MEI1IP 0 /* MEI #1 Pin */
+#define D20IP 0x3128 /* 32bit */
+#define D20IP_XHCIIP 0
+
+#define D31IR 0x3140 /* 16bit */
+#define D30IR 0x3142 /* 16bit */
+#define D29IR 0x3144 /* 16bit */
+#define D28IR 0x3146 /* 16bit */
+#define D27IR 0x3148 /* 16bit */
+#define D26IR 0x314c /* 16bit */
+#define D25IR 0x3150 /* 16bit */
+#define D23IR 0x3158 /* 16bit */
+#define D22IR 0x315c /* 16bit */
+#define D21IR 0x3164 /* 16bit */
+#define D20IR 0x3160 /* 16bit */
+#define D19IR 0x3168 /* 16bit */
+
+#define OIC 0x31ff /* 8bit */
+
+#define DIR_ROUTE(x, a, b, c, d) \
+ (RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+ ((b) << DIR_IBR) | ((a) << DIR_IAR)))
+
+#define RC 0x3400 /* 32bit */
+#define HPTC 0x3404 /* 32bit */
+#define GCS 0x3410 /* 32bit */
+#define BUC 0x3414 /* 32bit */
+#define PCH_DISABLE_GBE (1 << 5)
+#define FD 0x3418 /* 32bit */
+#define DISPBDF 0x3424 /* 16bit */
+#define FD2 0x3428 /* 32bit */
+#define CG 0x341c /* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
+#define PCH_DISABLE_P2P (1 << 1)
+#define PCH_DISABLE_SATA1 (1 << 2)
+#define PCH_DISABLE_SMBUS (1 << 3)
+#define PCH_DISABLE_HD_AUDIO (1 << 4)
+#define PCH_DISABLE_EHCI2 (1 << 13)
+#define PCH_DISABLE_LPC (1 << 14)
+#define PCH_DISABLE_EHCI1 (1 << 15)
+#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
+#define PCH_DISABLE_THERMAL (1 << 24)
+#define PCH_DISABLE_SATA2 (1 << 25)
+#define PCH_DISABLE_XHCI (1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT (1 << 4)
+#define PCH_DISABLE_IDER (1 << 3)
+#define PCH_DISABLE_MEI2 (1 << 2)
+#define PCH_DISABLE_MEI1 (1 << 1)
+#define PCH_ENABLE_DBDF (1 << 0)
+
+/* Function Disable (FD) register values.
+ * Setting a bit disables the corresponding
+ * feature.
+ * Not all features might be disabled on
+ * all chipsets. Esp. ICH-7U is picky.
+ */
+#define FD_PCIE6 (1 << 21)
+#define FD_PCIE5 (1 << 20)
+#define FD_PCIE4 (1 << 19)
+#define FD_PCIE3 (1 << 18)
+#define FD_PCIE2 (1 << 17)
+#define FD_PCIE1 (1 << 16)
+#define FD_EHCI (1 << 15)
+#define FD_LPCB (1 << 14)
+
+/* UHCI must be disabled from 4 downwards.
+ * If UHCI controllers get disabled, EHCI
+ * must know about it, too! */
+#define FD_UHCI4 (1 << 11)
+#define FD_UHCI34 ((1 << 10) | FD_UHCI4)
+#define FD_UHCI234 ((1 << 9) | FD_UHCI3)
+#define FD_UHCI1234 ((1 << 8) | FD_UHCI2)
+
+#define FD_INTLAN (1 << 7)
+#define FD_ACMOD (1 << 6)
+#define FD_ACAUD (1 << 5)
+#define FD_HDAUD (1 << 4)
+#define FD_SMBUS (1 << 3)
+#define FD_SATA (1 << 2)
+#define FD_PATA (1 << 1)
+
+#endif /* __ACPI__ */
+#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Gerrit-Change-Number: 23287
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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