<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23287">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/bd82x6: Move RCBA macros to a common location<br><br>Many generations of Intel hardware have identical code concerning the<br>RCBA.<br><br>Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_206ax/bootblock.c<br>M src/mainboard/asrock/b75pro3-m/mainboard.c<br>M src/mainboard/asrock/b75pro3-m/romstage.c<br>M src/mainboard/compulab/intense_pc/mainboard.c<br>M src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c<br>M src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c<br>M src/mainboard/google/beltino/lan.c<br>M src/mainboard/google/butterfly/acpi_tables.c<br>M src/mainboard/google/butterfly/chromeos.c<br>M src/mainboard/google/butterfly/mainboard.c<br>M src/mainboard/google/butterfly/mainboard_smi.c<br>M src/mainboard/google/link/acpi_tables.c<br>M src/mainboard/google/link/chromeos.c<br>M src/mainboard/google/link/i915.c<br>M src/mainboard/google/link/mainboard.c<br>M src/mainboard/google/link/mainboard_smi.c<br>M src/mainboard/google/parrot/acpi_tables.c<br>M src/mainboard/google/parrot/chromeos.c<br>M src/mainboard/google/parrot/mainboard.c<br>M src/mainboard/google/parrot/smihandler.c<br>M src/mainboard/google/stout/acpi_tables.c<br>M src/mainboard/google/stout/chromeos.c<br>M src/mainboard/google/stout/ec.c<br>M src/mainboard/google/stout/mainboard.c<br>M src/mainboard/google/stout/mainboard_smi.c<br>M src/mainboard/intel/emeraldlake2/chromeos.c<br>M src/mainboard/intel/emeraldlake2/mainboard.c<br>M src/mainboard/intel/emeraldlake2/smihandler.c<br>M src/mainboard/kontron/ktqm77/acpi_tables.c<br>M src/mainboard/kontron/ktqm77/mainboard.c<br>M src/mainboard/lenovo/l520/acpi_tables.c<br>M src/mainboard/lenovo/l520/smihandler.c<br>M src/mainboard/lenovo/s230u/smihandler.c<br>M src/mainboard/lenovo/t420/smihandler.c<br>M src/mainboard/lenovo/t420s/acpi_tables.c<br>M src/mainboard/lenovo/t420s/smihandler.c<br>M src/mainboard/lenovo/t430/smihandler.c<br>M src/mainboard/lenovo/t430s/smihandler.c<br>M src/mainboard/lenovo/t520/acpi_tables.c<br>M src/mainboard/lenovo/t520/smihandler.c<br>M src/mainboard/lenovo/t530/acpi_tables.c<br>M src/mainboard/lenovo/t530/smihandler.c<br>M src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c<br>M src/mainboard/lenovo/x1_carbon_gen1/romstage.c<br>M src/mainboard/lenovo/x1_carbon_gen1/smihandler.c<br>M src/mainboard/lenovo/x220/acpi_tables.c<br>M src/mainboard/lenovo/x220/smihandler.c<br>M src/mainboard/lenovo/x230/acpi_tables.c<br>M src/mainboard/lenovo/x230/smihandler.c<br>M src/mainboard/samsung/lumpy/chromeos.c<br>M src/mainboard/samsung/lumpy/mainboard.c<br>M src/mainboard/samsung/lumpy/smihandler.c<br>M src/mainboard/samsung/stumpy/chromeos.c<br>M src/mainboard/samsung/stumpy/mainboard.c<br>M src/mainboard/samsung/stumpy/smihandler.c<br>M src/northbridge/intel/sandybridge/early_init.c<br>M src/northbridge/intel/sandybridge/sandybridge.h<br>M src/southbridge/intel/bd82x6x/azalia.c<br>M src/southbridge/intel/bd82x6x/bootblock.c<br>M src/southbridge/intel/bd82x6x/early_pch.c<br>M src/southbridge/intel/bd82x6x/early_rcba.c<br>M src/southbridge/intel/bd82x6x/early_spi.c<br>M src/southbridge/intel/bd82x6x/early_thermal.c<br>M src/southbridge/intel/bd82x6x/finalize.c<br>M src/southbridge/intel/bd82x6x/lpc.c<br>M src/southbridge/intel/bd82x6x/me.c<br>M src/southbridge/intel/bd82x6x/me_8.x.c<br>M src/southbridge/intel/bd82x6x/pch.c<br>M src/southbridge/intel/bd82x6x/pch.h<br>M src/southbridge/intel/bd82x6x/pcie.c<br>M src/southbridge/intel/bd82x6x/smihandler.c<br>M src/southbridge/intel/bd82x6x/usb_ehci.c<br>A src/southbridge/intel/common/rcba.h<br>73 files changed, 290 insertions(+), 149 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/23287/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c</span><br><span>index 670b097..90215a4 100644</span><br><span>--- a/src/cpu/intel/model_206ax/bootblock.c</span><br><span>+++ b/src/cpu/intel/model_206ax/bootblock.c</span><br><span>@@ -28,6 +28,7 @@</span><br><span> IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)</span><br><span> /* Needed for RCBA access to set Soft Reset Data register */</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #else</span><br><span> #error "CPU must be paired with Intel BD82X6X or C216 southbridge"</span><br><span> #endif</span><br><span>diff --git a/src/mainboard/asrock/b75pro3-m/mainboard.c b/src/mainboard/asrock/b75pro3-m/mainboard.c</span><br><span>index f0d0cf7..76dea4e 100644</span><br><span>--- a/src/mainboard/asrock/b75pro3-m/mainboard.c</span><br><span>+++ b/src/mainboard/asrock/b75pro3-m/mainboard.c</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <drivers/intel/gma/int15.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> static void mainboard_enable(device_t dev)</span><br><span> {</span><br><span>diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c</span><br><span>index f556443..bde1cb4 100644</span><br><span>--- a/src/mainboard/asrock/b75pro3-m/romstage.c</span><br><span>+++ b/src/mainboard/asrock/b75pro3-m/romstage.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include "northbridge/intel/sandybridge/raminit_native.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <superio/nuvoton/nct6776/nct6776.h></span><br><span> #include <superio/nuvoton/common/nuvoton.h></span><br><span> </span><br><span>diff --git a/src/mainboard/compulab/intense_pc/mainboard.c b/src/mainboard/compulab/intense_pc/mainboard.c</span><br><span>index f06e900..d1c5d6a 100644</span><br><span>--- a/src/mainboard/compulab/intense_pc/mainboard.c</span><br><span>+++ b/src/mainboard/compulab/intense_pc/mainboard.c</span><br><span>@@ -16,6 +16,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <drivers/intel/gma/int15.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <ec/acpi/ec.h></span><br><span> #include <console/console.h></span><br><span> #include <pc80/keyboard.h></span><br><span>diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c</span><br><span>index bbf3241..d33dfc5 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c</span><br><span>index bbf3241..d33dfc5 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c</span><br><span>index 140c814..940b4de 100644</span><br><span>--- a/src/mainboard/google/beltino/lan.c</span><br><span>+++ b/src/mainboard/google/beltino/lan.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <fmap.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "onboard.h"</span><br><span> </span><br><span> static unsigned int search(char *p, u8 *a, unsigned int lengthp,</span><br><span>diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c</span><br><span>index e132232..3c867e3 100644</span><br><span>--- a/src/mainboard/google/butterfly/acpi_tables.c</span><br><span>+++ b/src/mainboard/google/butterfly/acpi_tables.c</span><br><span>@@ -28,6 +28,7 @@</span><br><span> #include <ec/quanta/ene_kb3940q/ec.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c</span><br><span>index 42f6189..f3bd518 100644</span><br><span>--- a/src/mainboard/google/butterfly/chromeos.c</span><br><span>+++ b/src/mainboard/google/butterfly/chromeos.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <device/pci.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <ec/quanta/ene_kb3940q/ec.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span>diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c</span><br><span>index a100981..3b2a460 100644</span><br><span>--- a/src/mainboard/google/butterfly/mainboard.c</span><br><span>+++ b/src/mainboard/google/butterfly/mainboard.c</span><br><span>@@ -31,6 +31,7 @@</span><br><span> #include "onboard.h"</span><br><span> #include "ec.h"</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <smbios.h></span><br><span> #include <device/pci.h></span><br><span> #include <ec/quanta/ene_kb3940q/ec.h></span><br><span>diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c</span><br><span>index 03e0316..8c64b10 100644</span><br><span>--- a/src/mainboard/google/butterfly/mainboard_smi.c</span><br><span>+++ b/src/mainboard/google/butterfly/mainboard_smi.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c</span><br><span>index 28d9922..3e7787e 100644</span><br><span>--- a/src/mainboard/google/link/acpi_tables.c</span><br><span>+++ b/src/mainboard/google/link/acpi_tables.c</span><br><span>@@ -29,6 +29,7 @@</span><br><span> </span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c</span><br><span>index 335f1f7..3cb7e1f 100644</span><br><span>--- a/src/mainboard/google/link/chromeos.c</span><br><span>+++ b/src/mainboard/google/link/chromeos.c</span><br><span>@@ -16,6 +16,7 @@</span><br><span> #include <string.h></span><br><span> #include <bootmode.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> </span><br><span>diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c</span><br><span>index 9ab3149..c1f834a 100644</span><br><span>--- a/src/mainboard/google/link/i915.c</span><br><span>+++ b/src/mainboard/google/link/i915.c</span><br><span>@@ -30,6 +30,7 @@</span><br><span> #include "onboard.h"</span><br><span> #include "ec.h"</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <northbridge/intel/sandybridge/gma.h></span><br><span> #include <smbios.h></span><br><span> #include <device/pci.h></span><br><span>diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c</span><br><span>index 24062e9..a2affcd 100644</span><br><span>--- a/src/mainboard/google/link/mainboard.c</span><br><span>+++ b/src/mainboard/google/link/mainboard.c</span><br><span>@@ -32,6 +32,7 @@</span><br><span> #include "onboard.h"</span><br><span> #include "ec.h"</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <smbios.h></span><br><span> #include <device/pci.h></span><br><span>diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c</span><br><span>index 0babb54..28c5cee 100644</span><br><span>--- a/src/mainboard/google/link/mainboard_smi.c</span><br><span>+++ b/src/mainboard/google/link/mainboard_smi.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c</span><br><span>index ae36ba0..e102d7c 100644</span><br><span>--- a/src/mainboard/google/parrot/acpi_tables.c</span><br><span>+++ b/src/mainboard/google/parrot/acpi_tables.c</span><br><span>@@ -29,6 +29,7 @@</span><br><span> #include "ec.h"</span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> #include "onboard.h"</span><br><span>diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c</span><br><span>index d2448eb..195b118 100644</span><br><span>--- a/src/mainboard/google/parrot/chromeos.c</span><br><span>+++ b/src/mainboard/google/parrot/chromeos.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <device/pci.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <ec/compal/ene932/ec.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span>diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c</span><br><span>index 4d357f8..9baac21 100644</span><br><span>--- a/src/mainboard/google/parrot/mainboard.c</span><br><span>+++ b/src/mainboard/google/parrot/mainboard.c</span><br><span>@@ -29,6 +29,7 @@</span><br><span> #include "onboard.h"</span><br><span> #include "ec.h"</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <smbios.h></span><br><span> #include <device/pci.h></span><br><span> #include <ec/compal/ene932/ec.h></span><br><span>diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c</span><br><span>index 176e33c..3dab9c9 100644</span><br><span>--- a/src/mainboard/google/parrot/smihandler.c</span><br><span>+++ b/src/mainboard/google/parrot/smihandler.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c</span><br><span>index 078cba2..72002a0 100644</span><br><span>--- a/src/mainboard/google/stout/acpi_tables.c</span><br><span>+++ b/src/mainboard/google/stout/acpi_tables.c</span><br><span>@@ -31,6 +31,7 @@</span><br><span> #include "onboard.h"</span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c</span><br><span>index 047e6a1..75255fe 100644</span><br><span>--- a/src/mainboard/google/stout/chromeos.c</span><br><span>+++ b/src/mainboard/google/stout/chromeos.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <device/pci.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> #include "ec.h"</span><br><span>diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c</span><br><span>index a459d0c..466e8be 100644</span><br><span>--- a/src/mainboard/google/stout/ec.c</span><br><span>+++ b/src/mainboard/google/stout/ec.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <elog.h></span><br><span> #include "ec.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c</span><br><span>index 4e3839f..4a4838a 100644</span><br><span>--- a/src/mainboard/google/stout/mainboard.c</span><br><span>+++ b/src/mainboard/google/stout/mainboard.c</span><br><span>@@ -29,6 +29,7 @@</span><br><span> #include "onboard.h"</span><br><span> #include "ec.h"</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <smbios.h></span><br><span> #include <device/pci.h></span><br><span> #include <ec/quanta/it8518/ec.h></span><br><span>diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c</span><br><span>index e25c576..9f368e1 100644</span><br><span>--- a/src/mainboard/google/stout/mainboard_smi.c</span><br><span>+++ b/src/mainboard/google/stout/mainboard_smi.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c</span><br><span>index eac995a..614c7f4 100644</span><br><span>--- a/src/mainboard/intel/emeraldlake2/chromeos.c</span><br><span>+++ b/src/mainboard/intel/emeraldlake2/chromeos.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> </span><br><span>diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c</span><br><span>index 654b1de..cdcde3d 100644</span><br><span>--- a/src/mainboard/intel/emeraldlake2/mainboard.c</span><br><span>+++ b/src/mainboard/intel/emeraldlake2/mainboard.c</span><br><span>@@ -28,6 +28,7 @@</span><br><span> #include <arch/interrupt.h></span><br><span> #include <boot/coreboot_tables.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> </span><br><span> // mainboard_enable is executed as first thing after</span><br><span>diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c</span><br><span>index 3662e6e..3cf2361 100644</span><br><span>--- a/src/mainboard/intel/emeraldlake2/smihandler.c</span><br><span>+++ b/src/mainboard/intel/emeraldlake2/smihandler.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c</span><br><span>index 312557c..c8b0006 100644</span><br><span>--- a/src/mainboard/kontron/ktqm77/acpi_tables.c</span><br><span>+++ b/src/mainboard/kontron/ktqm77/acpi_tables.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c</span><br><span>index 5a697f0..985a49d 100644</span><br><span>--- a/src/mainboard/kontron/ktqm77/mainboard.c</span><br><span>+++ b/src/mainboard/kontron/ktqm77/mainboard.c</span><br><span>@@ -30,6 +30,7 @@</span><br><span> #include <arch/interrupt.h></span><br><span> #include <boot/coreboot_tables.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_VGA_ROM_RUN)</span><br><span> static int int15_handler(void)</span><br><span>diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c</span><br><span>index 9ce40fb..a1191f3 100644</span><br><span>--- a/src/mainboard/lenovo/l520/acpi_tables.c</span><br><span>+++ b/src/mainboard/lenovo/l520/acpi_tables.c</span><br><span>@@ -16,6 +16,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c</span><br><span>index f0c7a04..831ddd5 100644</span><br><span>--- a/src/mainboard/lenovo/l520/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/l520/smihandler.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <ec/acpi/ec.h></span><br><span> #include <ec/lenovo/h8/h8.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define GPE_EC_SCI 6</span><br><span> /* FIXME: check this */</span><br><span>diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c</span><br><span>index 755f176..3be54f9 100644</span><br><span>--- a/src/mainboard/lenovo/s230u/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/s230u/smihandler.c</span><br><span>@@ -25,6 +25,7 @@</span><br><span> #include <ec/acpi/ec.h></span><br><span> #include <ec/compal/ene932/ec.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define GPE_PALMDET1 2</span><br><span> #define GPE_PALMDET2 4</span><br><span>diff --git a/src/mainboard/lenovo/t420/smihandler.c b/src/mainboard/lenovo/t420/smihandler.c</span><br><span>index 825a20b..93a7115 100644</span><br><span>--- a/src/mainboard/lenovo/t420/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/t420/smihandler.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <ec/acpi/ec.h></span><br><span> #include <ec/lenovo/h8/h8.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define GPE_EC_SCI 1</span><br><span> #define GPE_EC_WAKE 13</span><br><span>diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c</span><br><span>index 1a6cb83..7b05945 100644</span><br><span>--- a/src/mainboard/lenovo/t420s/acpi_tables.c</span><br><span>+++ b/src/mainboard/lenovo/t420s/acpi_tables.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c</span><br><span>index 471095e..f198a81 100644</span><br><span>--- a/src/mainboard/lenovo/t420s/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/t420s/smihandler.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <delay.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c</span><br><span>index 7af9e7d..d38d60e 100644</span><br><span>--- a/src/mainboard/lenovo/t430/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/t430/smihandler.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <ec/lenovo/h8/h8.h></span><br><span> #include <delay.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define GPE_EC_SCI 1</span><br><span> #define GPE_EC_WAKE 13</span><br><span>diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c</span><br><span>index 512e631..786827c 100644</span><br><span>--- a/src/mainboard/lenovo/t430s/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/t430s/smihandler.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <ec/lenovo/h8/h8.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c</span><br><span>index b1c4733..7e8d436 100644</span><br><span>--- a/src/mainboard/lenovo/t520/acpi_tables.c</span><br><span>+++ b/src/mainboard/lenovo/t520/acpi_tables.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c</span><br><span>index 3fa8e30..371482d 100644</span><br><span>--- a/src/mainboard/lenovo/t520/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/t520/smihandler.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <delay.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c</span><br><span>index b1c4733..7e8d436 100644</span><br><span>--- a/src/mainboard/lenovo/t530/acpi_tables.c</span><br><span>+++ b/src/mainboard/lenovo/t530/acpi_tables.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c</span><br><span>index 1dfd87e..bf94b10 100644</span><br><span>--- a/src/mainboard/lenovo/t530/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/t530/smihandler.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <delay.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c</span><br><span>index 2c148d4..889290d 100644</span><br><span>--- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c</span><br><span>+++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c</span><br><span>@@ -28,6 +28,7 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c</span><br><span>index 5f7b82e..48bf6a5 100644</span><br><span>--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c</span><br><span>@@ -32,6 +32,7 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/cpu.h></span><br><span> #include <cpu/x86/msr.h></span><br><span>diff --git a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c</span><br><span>index 09dcbf2..0b87f06 100644</span><br><span>--- a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <ec/acpi/ec.h></span><br><span> #include <ec/lenovo/h8/h8.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define GPE_EC_SCI 1</span><br><span> #define GPE_EC_WAKE 13</span><br><span>diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c</span><br><span>index c9e9407..7245529 100644</span><br><span>--- a/src/mainboard/lenovo/x220/acpi_tables.c</span><br><span>+++ b/src/mainboard/lenovo/x220/acpi_tables.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c</span><br><span>index 1dfd87e..bf94b10 100644</span><br><span>--- a/src/mainboard/lenovo/x220/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/x220/smihandler.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <delay.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c</span><br><span>index c9e9407..7245529 100644</span><br><span>--- a/src/mainboard/lenovo/x230/acpi_tables.c</span><br><span>+++ b/src/mainboard/lenovo/x230/acpi_tables.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include "thermal.h"</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c</span><br><span>index 4572cae..62700d9 100644</span><br><span>--- a/src/mainboard/lenovo/x230/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/x230/smihandler.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <ec/acpi/ec.h></span><br><span> #include <ec/lenovo/h8/h8.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define GPE_EC_SCI 1</span><br><span> #define GPE_EC_WAKE 13</span><br><span>diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c</span><br><span>index a287c74..b1e0b2e 100644</span><br><span>--- a/src/mainboard/samsung/lumpy/chromeos.c</span><br><span>+++ b/src/mainboard/samsung/lumpy/chromeos.c</span><br><span>@@ -20,6 +20,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> </span><br><span>diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c</span><br><span>index 3de067e..5f6bd8a 100644</span><br><span>--- a/src/mainboard/samsung/lumpy/mainboard.c</span><br><span>+++ b/src/mainboard/samsung/lumpy/mainboard.c</span><br><span>@@ -30,6 +30,7 @@</span><br><span> #include "ec.h"</span><br><span> #include "onboard.h"</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <smbios.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> </span><br><span>diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c</span><br><span>index 9690aee..7df6b07 100644</span><br><span>--- a/src/mainboard/samsung/lumpy/smihandler.c</span><br><span>+++ b/src/mainboard/samsung/lumpy/smihandler.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c</span><br><span>index 01d81d7..c67fd9a 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/chromeos.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/chromeos.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> </span><br><span>diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c</span><br><span>index 654b1de..cdcde3d 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/mainboard.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/mainboard.c</span><br><span>@@ -28,6 +28,7 @@</span><br><span> #include <arch/interrupt.h></span><br><span> #include <boot/coreboot_tables.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> </span><br><span> // mainboard_enable is executed as first thing after</span><br><span>diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c</span><br><span>index 00148f2..2240d69 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/smihandler.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/smihandler.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <southbridge/intel/bd82x6x/nvs.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <southbridge/intel/bd82x6x/me.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span>diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c</span><br><span>index 2f1b790..612e25b 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/early_init.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/early_init.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <cbmem.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span> #include <romstage_handoff.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "sandybridge.h"</span><br><span> </span><br><span> static void sandybridge_setup_bars(void)</span><br><span>diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>index dd1a58c..2f844bc 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>+++ b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>@@ -58,6 +58,7 @@</span><br><span> #define IOMMU_BASE2 0xfed91000ULL</span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> /* Everything below this line is ignored in the DSDT */</span><br><span> #ifndef __ACPI__</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c</span><br><span>index 9c8eaf6..02165d6 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/azalia.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/azalia.c</span><br><span>@@ -23,6 +23,7 @@</span><br><span> #include <arch/io.h></span><br><span> #include <delay.h></span><br><span> #include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span> #define HDA_ICII_REG 0x68</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c</span><br><span>index 8541903..b3a1911 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/bootblock.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/bootblock.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <cpu/x86/tsc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "southbridge/intel/common/rcba.h"</span><br><span> #include "pch.h"</span><br><span> </span><br><span> static void store_initial_timestamp(void)</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c</span><br><span>index 4015495..427e58c 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_pch.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_pch.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include <delay.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> /* For DMI bar. */</span><br><span> #include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>index eeecb5f..190a7c1 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>@@ -17,6 +17,7 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include "pch.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span> </span><br><span> void</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c</span><br><span>index 1400837..a9ecd82 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_spi.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_spi.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span> #define SPI_DELAY 10 /* 10us */</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c</span><br><span>index a5c63b6..37df501 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_thermal.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_thermal.c</span><br><span>@@ -16,6 +16,7 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include "pch.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "cpu/intel/model_206ax/model_206ax.h"</span><br><span> #include <cpu/x86/msr.h></span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>index fe28af0..6b38fcd 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <arch/io.h></span><br><span> #include <console/post_codes.h></span><br><span> #include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> #include <spi-generic.h></span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>index 7f61669..4212d1a 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>@@ -32,6 +32,7 @@</span><br><span> #include <cbmem.h></span><br><span> #include <string.h></span><br><span> #include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> #include "nvs.h"</span><br><span> #include <southbridge/intel/common/pciehp.h></span><br><span>diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c</span><br><span>index 70ba301..a5c5e52 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/me.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/me.c</span><br><span>@@ -39,6 +39,7 @@</span><br><span> # include <device/pci.h></span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "me.h"</span><br><span> #include "pch.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>index 2e29233..6463f96 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>@@ -39,6 +39,7 @@</span><br><span> # include <device/pci.h></span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "me.h"</span><br><span> #include "pch.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c</span><br><span>index 0b0fc35..73c84bb 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #endif</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> #include <string.h></span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index 83d9d8d..78ceb22 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -45,12 +45,6 @@</span><br><span> #define DEFAULT_GPIOBASE 0x0480</span><br><span> #define DEFAULT_PMBASE 0x0500</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)</span><br><span> #define CROS_GPIO_DEVICE_NAME "CougarPoint"</span><br><span> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)</span><br><span>@@ -277,73 +271,6 @@</span><br><span> /* Root Complex Register Block */</span><br><span> #define RCBA 0xf0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCH 0x0000 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCAP1 0x0004 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define VCAP2 0x0008 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PVC 0x000c /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PVS 0x000e /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define V0CAP 0x0010 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define V0CTL 0x0014 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define V0STS 0x001a /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define V1CAP 0x001c /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define V1CTL 0x0020 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define V1STS 0x0026 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCTCL 0x0100 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ESD 0x0104 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ULD 0x0110 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ULBA 0x0118 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP1D 0x0120 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP1BA 0x0128 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP2D 0x0130 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP2BA 0x0138 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP3D 0x0140 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP3BA 0x0148 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP4D 0x0150 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP4BA 0x0158 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDD 0x0160 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDBA 0x0168 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP5D 0x0170 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP5BA 0x0178 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP6D 0x0180 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RP6BA 0x0188 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPC 0x0400 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN 0x0404 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Port configuratinon space hide */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))</span><br><span style="color: hsl(0, 100%, 40%);">-/* Get the function number assigned to a Root Port */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)</span><br><span style="color: hsl(0, 100%, 40%);">-/* Set the function number for a Root Port */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))</span><br><span style="color: hsl(0, 100%, 40%);">-/* Root Port function number mask */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RPFN_FNMASK(port) (7 << ((port) * 4))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRSR 0x1e00 /* 8bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRCR 0x1e10 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define TWDR 0x1e18 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOTR0 0x1e80 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOTR1 0x1e88 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOTR2 0x1e90 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOTR3 0x1e98 /* 64bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCTL 0x3000 /* 8bit */</span><br><span> </span><br><span> #define NOINT 0</span><br><span> #define INTA 1</span><br><span>@@ -373,85 +300,9 @@</span><br><span> #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))</span><br><span> #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP 0x3100 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP_TTIP 24 /* Thermal Throttle Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP_SIP2 20 /* SATA Pin 2 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP_SMIP 12 /* SMBUS Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IP_SIP 8 /* SATA Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D30IP 0x3104 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D30IP_PIP 0 /* PCI Bridge Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D29IP 0x3108 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D29IP_E1P 0 /* EHCI #1 Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP 0x310c /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P8IP 28 /* PCI Express Port 8 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P7IP 24 /* PCI Express Port 7 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P6IP 20 /* PCI Express Port 6 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P5IP 16 /* PCI Express Port 5 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P4IP 12 /* PCI Express Port 4 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P3IP 8 /* PCI Express Port 3 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P2IP 4 /* PCI Express Port 2 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IP_P1IP 0 /* PCI Express Port 1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D27IP 0x3110 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D27IP_ZIP 0 /* HD Audio Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D26IP 0x3114 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D26IP_E2P 0 /* EHCI #2 Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D25IP 0x3118 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D25IP_LIP 0 /* GbE LAN Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP 0x3124 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP_KTIP 12 /* KT Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP_IDERIP 8 /* IDE-R Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP_MEI2IP 4 /* MEI #2 Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IP_MEI1IP 0 /* MEI #1 Pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D20IP 0x3128 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D20IP_XHCIIP 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define D31IR 0x3140 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D30IR 0x3142 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D29IR 0x3144 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D28IR 0x3146 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D27IR 0x3148 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D26IR 0x314c /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D25IR 0x3150 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D22IR 0x315c /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define D20IR 0x3160 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define OIC 0x31fe /* 16bit */</span><br><span> #define SOFT_RESET_CTRL 0x38f4</span><br><span> #define SOFT_RESET_DATA 0x38f8</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define DIR_ROUTE(x,a,b,c,d) \</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \</span><br><span style="color: hsl(0, 100%, 40%);">- ((b) << DIR_IBR) | ((a) << DIR_IAR))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RC 0x3400 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HPTC 0x3404 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GCS 0x3410 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define BUC 0x3414 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_GBE (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD 0x3418 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DISPBDF 0x3424 /* 16bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD2 0x3428 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG 0x341c /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Function Disable 1 RCBA 0x3418 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_P2P (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_SATA1 (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_SMBUS (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_HD_AUDIO (1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_EHCI2 (1 << 13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_LPC (1 << 14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_EHCI1 (1 << 15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_PCIE(x) (1 << (16 + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_THERMAL (1 << 24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_SATA2 (1 << 25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_XHCI (1 << 27)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Function Disable 2 RCBA 0x3428 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_KT (1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_IDER (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_MEI2 (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DISABLE_MEI1 (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_ENABLE_DBDF (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* USB Port Disable Override */</span><br><span> #define USBPDO 0x359c /* 32bit */</span><br><span> /* USB Overcurrent MAP Register */</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c</span><br><span>index 34b7694..1f4c157 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pcie.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pcie.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> #include <southbridge/intel/common/pciehp.h></span><br><span> #include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span> static void pch_pcie_pm_early(struct device *dev)</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>index 165acab..bf72b5e 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>@@ -23,6 +23,7 @@</span><br><span> #include <elog.h></span><br><span> #include <halt.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span> #include "nvs.h"</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c</span><br><span>index 90b29c4..b5ce820 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/usb_ehci.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> #include <device/pci_ehci.h></span><br><span> #include <arch/io.h></span><br><span>diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h</span><br><span>new file mode 100644</span><br><span>index 0000000..1399fde</span><br><span>--- /dev/null</span><br><span>+++ b/src/southbridge/intel/common/rcba.h</span><br><span>@@ -0,0 +1,219 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The DnnIR registers use common RCBA offsets across these chipsets:</span><br><span style="color: hsl(120, 100%, 40%);">+ * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * However not all registers are in use on all of these.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(120, 100%, 40%);">+ (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCH 0x0000 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCAP1 0x0004 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define VCAP2 0x0008 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PVC 0x000c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PVS 0x000e /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define V0CAP 0x0010 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V0CTL 0x0014 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V0STS 0x001a /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define V1CAP 0x001c /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V1CTL 0x0020 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define V1STS 0x0026 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCTCL 0x0100 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ESD 0x0104 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ULD 0x0110 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ULBA 0x0118 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP1D 0x0120 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP1BA 0x0128 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP2D 0x0130 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP2BA 0x0138 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP3D 0x0140 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP3BA 0x0148 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP4D 0x0150 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP4BA 0x0158 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDD 0x0160 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDBA 0x0168 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP5D 0x0170 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP5BA 0x0178 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP6D 0x0180 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RP6BA 0x0188 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPC 0x0400 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN 0x0404 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Root Port configuratinon space hide */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get the function number assigned to a Root Port */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set the function number for a Root Port */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+/* Root Port function number mask */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNMASK(port) (7 << ((port) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRSR 0x1e00 /* 8bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TRCR 0x1e10 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TWDR 0x1e18 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR0 0x1e80 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR1 0x1e88 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR2 0x1e90 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOTR3 0x1e98 /* 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCTL 0x3000 /* 8bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP 0x3100 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_TTIP 24 /* Thermal Throttle Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_SIP2 20 /* SATA Pin 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_SMIP 12 /* SMBUS Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IP_SIP 8 /* SATA Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IP 0x3104 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IP_PIP 0 /* PCI Bridge Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IP 0x3108 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IP_E1P 0 /* EHCI #1 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP 0x310c /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P8IP 28 /* PCI Express Port 8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P7IP 24 /* PCI Express Port 7 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P6IP 20 /* PCI Express Port 6 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P5IP 16 /* PCI Express Port 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P4IP 12 /* PCI Express Port 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P3IP 8 /* PCI Express Port 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P2IP 4 /* PCI Express Port 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IP_P1IP 0 /* PCI Express Port 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IP 0x3110 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IP_ZIP 0 /* HD Audio Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IP 0x3114 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IP_E2P 0 /* EHCI #2 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IP 0x3118 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IP_LIP 0 /* GbE LAN Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP 0x3124 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_KTIP 12 /* KT Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_IDERIP 8 /* IDE-R Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_MEI2IP 4 /* MEI #2 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IP_MEI1IP 0 /* MEI #1 Pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IP 0x3128 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IP_XHCIIP 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31IR 0x3140 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D30IR 0x3142 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D29IR 0x3144 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D28IR 0x3146 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D27IR 0x3148 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D26IR 0x314c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D25IR 0x3150 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D23IR 0x3158 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D22IR 0x315c /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D21IR 0x3164 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D20IR 0x3160 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define D19IR 0x3168 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define OIC 0x31ff /* 8bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIR_ROUTE(x, a, b, c, d) \</span><br><span style="color: hsl(120, 100%, 40%);">+ (RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((b) << DIR_IBR) | ((a) << DIR_IAR)))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RC 0x3400 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HPTC 0x3404 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCS 0x3410 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define BUC 0x3414 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_GBE (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD 0x3418 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISPBDF 0x3424 /* 16bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD2 0x3428 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG 0x341c /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Function Disable 1 RCBA 0x3418 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_P2P (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_SATA1 (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_SMBUS (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_HD_AUDIO (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_EHCI2 (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_LPC (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_EHCI1 (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_PCIE(x) (1 << (16 + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_THERMAL (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_SATA2 (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_XHCI (1 << 27)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Function Disable 2 RCBA 0x3428 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_KT (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_IDER (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_MEI2 (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DISABLE_MEI1 (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_ENABLE_DBDF (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Function Disable (FD) register values.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Setting a bit disables the corresponding</span><br><span style="color: hsl(120, 100%, 40%);">+ * feature.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Not all features might be disabled on</span><br><span style="color: hsl(120, 100%, 40%);">+ * all chipsets. Esp. ICH-7U is picky.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_PCIE6 (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_PCIE5 (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_PCIE4 (1 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_PCIE3 (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_PCIE2 (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_PCIE1 (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_EHCI (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_LPCB (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* UHCI must be disabled from 4 downwards.</span><br><span style="color: hsl(120, 100%, 40%);">+ * If UHCI controllers get disabled, EHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ * must know about it, too! */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_UHCI4 (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_UHCI34 ((1 << 10) | FD_UHCI4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_UHCI234 ((1 << 9) | FD_UHCI3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_UHCI1234 ((1 << 8) | FD_UHCI2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_INTLAN (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_ACMOD (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_ACAUD (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_HDAUD (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_SMBUS (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_SATA (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_PATA (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __ACPI__ */</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23287">change 23287</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23287"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a </div>
<div style="display:none"> Gerrit-Change-Number: 23287 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>