[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Set PsysPmax value
Gaggery Tsai (Code Review)
gerrit at coreboot.org
Mon Jan 15 08:50:58 CET 2018
Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/23268
Change subject: soc/intel/skylake: Set PsysPmax value
......................................................................
soc/intel/skylake: Set PsysPmax value
According to doc #543977 Power Architecture Guide, PsysPmax equals
to PL4 + Prop where Prop stands for "Reset of Platform" power and
PL4 is well-defined in document. This patch adds a "prop" member in
chip information which allows boards to setup Prop power in device
tree. PsysPmax value is calculated and passed to FSP through UPD.
Besides, move some common code from vr_config.c to common.c.
BUG=b:71594855
BRANCH=None
TEST=Set prop in device tree & "USE=fw_debug emerge-fizz chromeos-mrc
coreboot chromeos-bootimage" & ensure correct PsysPmax value is
calculated and passed to FSP-S through UPD. Verfied on KBL-R and
KBL-U SKUs.
Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883
Signed-off-by: Gaggery Tsai <gaggery.tsai at intel.com>
---
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
A src/soc/intel/skylake/common.c
A src/soc/intel/skylake/common.h
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/include/soc/cpu.h
M src/soc/intel/skylake/vr_config.c
8 files changed, 144 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/23268/1
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index ef95cf7..bd96f3b 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -65,6 +65,7 @@
ramstage-y += thermal.c
ramstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-y += vr_config.c
+ramstage-y += common.c
smm-y += elog.c
smm-y += gpio.c
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 4e8cb81..3aa09fc 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -100,6 +100,9 @@
/* SysPL2 Value in Watts */
u32 tdp_psyspl2;
+ /* Rest of Platform power */
+ u16 prop;
+
/*
* The following fields come from FspUpdVpd.h.
* These are configuration values that are passed to FSP during
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index ccda303..0d0d162 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -28,6 +28,7 @@
#include <fsp/util.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
+#include <soc/cpu.h>
#include <soc/intel/common/vbt.h>
#include <soc/interrupt.h>
#include <soc/irq.h>
@@ -93,7 +94,7 @@
FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
static struct soc_intel_skylake_config *config;
uintptr_t vbt_data = 0;
-
+ uint16_t psys_pmax;
int i;
int is_s3_wakeup = acpi_is_wakeup_s3();
@@ -106,6 +107,13 @@
config = dev->chip_info;
mainboard_silicon_init_params(params);
+ /* Set PsysPmax if Prop is declared */
+ if (config->prop){
+ psys_pmax = get_psys_pmax(config->prop);
+ /* Set PsysPmax value if the detected SKU is in our support list */
+ if (psys_pmax)
+ tconfig->PsysPmax = psys_pmax;
+ }
/* Load VBT */
if (is_s3_wakeup) {
diff --git a/src/soc/intel/skylake/common.c b/src/soc/intel/skylake/common.c
new file mode 100644
index 0000000..d66dac0
--- /dev/null
+++ b/src/soc/intel/skylake/common.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <common.h>
+#include <soc/pci_devs.h>
+#include <device/pci_ids.h>
+
+uint16_t get_dev_id(device_t dev)
+{
+ return pci_read_config16(dev, PCI_DEVICE_ID);
+}
+
+int get_kbl_sku(void)
+{
+ static int sku = -1;
+ uint16_t id;
+
+ if (sku != -1)
+ return sku;
+
+ id = get_dev_id(SA_DEV_ROOT);
+ if (id == PCI_DEVICE_ID_INTEL_KBL_U_R)
+ sku = KBL_R_SKU;
+ else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y)
+ sku = KBL_Y_SKU;
+ else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) {
+ id = get_dev_id(PCH_DEV_LPC);
+ if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22)
+ sku = KBL_U_BASE_SKU;
+ else
+ sku = KBL_U_PREMIUM_SKU;
+ } else
+ /* Not one of the skus with available Icc max mapping. */
+ sku = -2;
+ return sku;
+}
+
diff --git a/src/soc/intel/skylake/common.h b/src/soc/intel/skylake/common.h
new file mode 100644
index 0000000..cb0feab
--- /dev/null
+++ b/src/soc/intel/skylake/common.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef _SOC_COMMON_H_
+#define _SOC_COMMON_H_
+
+enum kbl_sku {
+ KBL_Y_SKU,
+ KBL_R_SKU,
+ KBL_U_BASE_SKU,
+ KBL_U_PREMIUM_SKU,
+};
+
+uint16_t get_dev_id(device_t dev);
+int get_kbl_sku(void);
+
+#endif
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 291a40d..6f52463 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -22,6 +22,7 @@
#include <device/pci.h>
#include <string.h>
#include <chip.h>
+#include "common.h"
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
@@ -106,6 +107,28 @@
[0x11] = 128,
};
+static const struct {
+ enum kbl_sku sku;
+ uint32_t pl4;
+}sku_pl4_mapping[] = {
+ [KBL_Y_SKU] = {
+ .sku = KBL_Y_SKU,
+ .pl4 = 30,
+ },
+ [KBL_R_SKU] = {
+ .sku = KBL_R_SKU,
+ .pl4 = 71,
+ },
+ [KBL_U_BASE_SKU] = {
+ .sku = KBL_U_BASE_SKU,
+ .pl4 = 43,
+ },
+ [KBL_U_PREMIUM_SKU] = {
+ .sku = KBL_U_PREMIUM_SKU,
+ .pl4 = 43,
+ },
+};
+
/*
* Configure processor power limits if possible
* This must be done AFTER set of BIOS_RESET_CPL
@@ -520,3 +543,25 @@
sgx_param->enable = conf->sgx_enable;
return 0;
}
+
+/* This function calculate psys_pmax value for each SKU.
+ * According doc # 543977, PsysPmax = PL4 + Prop
+ * Table 8-1 Power levels (PLx) for different SKUs
+ * +---------+--------+
+ * | SKU | PL4 (W)|
+ * +---------+--------+
+ * | Y22 4W | 30 |
+ * +---------+--------+
+ * | U22 15W | 43 |
+ * +---------+--------+
+ * | U42 15W | 71 |
+ * +---------+--------+
+ */
+u16 get_psys_pmax(u16 prop)
+{
+ /* Check if this SKU has a mapping table entry. */
+ int sku_id = get_kbl_sku();
+ if (sku_id < 0)
+ return 0;
+ return (sku_pl4_mapping[sku_id].pl4 + prop);
+}
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index 8073fcd..e68707d 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -57,4 +57,7 @@
u32 cpu_stepping(void);
int cpu_is_ult(void);
+/* Calculate Psys Pmax value */
+u16 get_psys_pmax(u16 prop);
+
#endif
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 053e793..681a2e3 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include "common.h"
#include <device/pci_ids.h>
#include <fsp/api.h>
#include <soc/ramstage.h>
@@ -30,13 +31,6 @@
#define KBLU_ICCMAX_CORE_U22_BASE VR_CFG_AMP(29)
#define KBLUR_ICCMAX_GTS_GTUS VR_CFG_AMP(31)
-enum kbl_sku {
- KBL_Y_SKU,
- KBL_R_SKU,
- KBL_U_BASE_SKU,
- KBL_U_PREMIUM_SKU,
-};
-
/*
* Iccmax table from Doc #559100 Section 7.2 DC Specifications, the
* Iccmax is the same among KBL-Y but KBL-U/R.
@@ -159,36 +153,6 @@
},
};
-static uint16_t get_dev_id(device_t dev)
-{
- return pci_read_config16(dev, PCI_DEVICE_ID);
-}
-
-static int get_kbl_sku(void)
-{
- static int sku = -1;
- uint16_t id;
-
- if (sku != -1)
- return sku;
-
- id = get_dev_id(SA_DEV_ROOT);
- if (id == PCI_DEVICE_ID_INTEL_KBL_U_R)
- sku = KBL_R_SKU;
- else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y)
- sku = KBL_Y_SKU;
- else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) {
- id = get_dev_id(PCH_DEV_LPC);
- if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22)
- sku = KBL_U_BASE_SKU;
- else
- sku = KBL_U_PREMIUM_SKU;
- } else
- /* Not one of the skus with available Icc max mapping. */
- sku = -2;
- return sku;
-}
-
static uint16_t get_sku_icc_max(int domain, uint16_t board_icc_max)
{
/* If board provided non-zero value, use it. */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883
Gerrit-Change-Number: 23268
Gerrit-PatchSet: 1
Gerrit-Owner: Gaggery Tsai <gaggery.tsai at intel.com>
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