<p>Gaggery Tsai has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23268">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Set PsysPmax value<br><br>According to doc #543977 Power Architecture Guide, PsysPmax equals<br>to PL4 + Prop where Prop stands for "Reset of Platform" power and<br>PL4 is well-defined in document. This patch adds a "prop" member in<br>chip information which allows boards to setup Prop power in device<br>tree. PsysPmax value is calculated and passed to FSP through UPD.<br>Besides, move some common code from vr_config.c to common.c.<br><br>BUG=b:71594855<br>BRANCH=None<br>TEST=Set prop in device tree & "USE=fw_debug emerge-fizz chromeos-mrc<br> coreboot chromeos-bootimage" & ensure correct PsysPmax value is<br> calculated and passed to FSP-S through UPD. Verfied on KBL-R and<br> KBL-U SKUs.<br><br>Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883<br>Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com><br>---<br>M src/soc/intel/skylake/Makefile.inc<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>A src/soc/intel/skylake/common.c<br>A src/soc/intel/skylake/common.h<br>M src/soc/intel/skylake/cpu.c<br>M src/soc/intel/skylake/include/soc/cpu.h<br>M src/soc/intel/skylake/vr_config.c<br>8 files changed, 144 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/23268/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc</span><br><span>index ef95cf7..bd96f3b 100644</span><br><span>--- a/src/soc/intel/skylake/Makefile.inc</span><br><span>+++ b/src/soc/intel/skylake/Makefile.inc</span><br><span>@@ -65,6 +65,7 @@</span><br><span> ramstage-y += thermal.c</span><br><span> ramstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> ramstage-y += vr_config.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += common.c</span><br><span> </span><br><span> smm-y += elog.c</span><br><span> smm-y += gpio.c</span><br><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index 4e8cb81..3aa09fc 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -100,6 +100,9 @@</span><br><span> /* SysPL2 Value in Watts */</span><br><span> u32 tdp_psyspl2;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rest of Platform power */</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 prop;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * The following fields come from FspUpdVpd.h.</span><br><span> * These are configuration values that are passed to FSP during</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index ccda303..0d0d162 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -28,6 +28,7 @@</span><br><span> #include <fsp/util.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <soc/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cpu.h></span><br><span> #include <soc/intel/common/vbt.h></span><br><span> #include <soc/interrupt.h></span><br><span> #include <soc/irq.h></span><br><span>@@ -93,7 +94,7 @@</span><br><span> FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;</span><br><span> static struct soc_intel_skylake_config *config;</span><br><span> uintptr_t vbt_data = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t psys_pmax;</span><br><span> int i;</span><br><span> </span><br><span> int is_s3_wakeup = acpi_is_wakeup_s3();</span><br><span>@@ -106,6 +107,13 @@</span><br><span> config = dev->chip_info;</span><br><span> </span><br><span> mainboard_silicon_init_params(params);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set PsysPmax if Prop is declared */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->prop){</span><br><span style="color: hsl(120, 100%, 40%);">+ psys_pmax = get_psys_pmax(config->prop);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set PsysPmax value if the detected SKU is in our support list */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (psys_pmax)</span><br><span style="color: hsl(120, 100%, 40%);">+ tconfig->PsysPmax = psys_pmax;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> /* Load VBT */</span><br><span> if (is_s3_wakeup) {</span><br><span>diff --git a/src/soc/intel/skylake/common.c b/src/soc/intel/skylake/common.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d66dac0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/skylake/common.c</span><br><span>@@ -0,0 +1,51 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint16_t get_dev_id(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config16(dev, PCI_DEVICE_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_kbl_sku(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static int sku = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t id;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sku != -1)</span><br><span style="color: hsl(120, 100%, 40%);">+ return sku;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ id = get_dev_id(SA_DEV_ROOT);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (id == PCI_DEVICE_ID_INTEL_KBL_U_R)</span><br><span style="color: hsl(120, 100%, 40%);">+ sku = KBL_R_SKU;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y)</span><br><span style="color: hsl(120, 100%, 40%);">+ sku = KBL_Y_SKU;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) {</span><br><span style="color: hsl(120, 100%, 40%);">+ id = get_dev_id(PCH_DEV_LPC);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22)</span><br><span style="color: hsl(120, 100%, 40%);">+ sku = KBL_U_BASE_SKU;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ sku = KBL_U_PREMIUM_SKU;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Not one of the skus with available Icc max mapping. */</span><br><span style="color: hsl(120, 100%, 40%);">+ sku = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ return sku;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/soc/intel/skylake/common.h b/src/soc/intel/skylake/common.h</span><br><span>new file mode 100644</span><br><span>index 0000000..cb0feab</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/skylake/common.h</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_COMMON_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_COMMON_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum kbl_sku {</span><br><span style="color: hsl(120, 100%, 40%);">+ KBL_Y_SKU,</span><br><span style="color: hsl(120, 100%, 40%);">+ KBL_R_SKU,</span><br><span style="color: hsl(120, 100%, 40%);">+ KBL_U_BASE_SKU,</span><br><span style="color: hsl(120, 100%, 40%);">+ KBL_U_PREMIUM_SKU,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint16_t get_dev_id(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+int get_kbl_sku(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c</span><br><span>index 291a40d..6f52463 100644</span><br><span>--- a/src/soc/intel/skylake/cpu.c</span><br><span>+++ b/src/soc/intel/skylake/cpu.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <string.h></span><br><span> #include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "common.h"</span><br><span> #include <cpu/cpu.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/x86/msr.h></span><br><span>@@ -106,6 +107,28 @@</span><br><span> [0x11] = 128,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ enum kbl_sku sku;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pl4;</span><br><span style="color: hsl(120, 100%, 40%);">+}sku_pl4_mapping[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [KBL_Y_SKU] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .sku = KBL_Y_SKU,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pl4 = 30,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [KBL_R_SKU] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .sku = KBL_R_SKU,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pl4 = 71,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [KBL_U_BASE_SKU] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .sku = KBL_U_BASE_SKU,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pl4 = 43,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [KBL_U_PREMIUM_SKU] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .sku = KBL_U_PREMIUM_SKU,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pl4 = 43,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * Configure processor power limits if possible</span><br><span> * This must be done AFTER set of BIOS_RESET_CPL</span><br><span>@@ -520,3 +543,25 @@</span><br><span> sgx_param->enable = conf->sgx_enable;</span><br><span> return 0;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* This function calculate psys_pmax value for each SKU.</span><br><span style="color: hsl(120, 100%, 40%);">+ * According doc # 543977, PsysPmax = PL4 + Prop</span><br><span style="color: hsl(120, 100%, 40%);">+ * Table 8-1 Power levels (PLx) for different SKUs</span><br><span style="color: hsl(120, 100%, 40%);">+ * +---------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | SKU | PL4 (W)|</span><br><span style="color: hsl(120, 100%, 40%);">+ * +---------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | Y22 4W | 30 |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +---------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | U22 15W | 43 |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +---------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | U42 15W | 71 |</span><br><span style="color: hsl(120, 100%, 40%);">+ * +---------+--------+</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+u16 get_psys_pmax(u16 prop)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Check if this SKU has a mapping table entry. */</span><br><span style="color: hsl(120, 100%, 40%);">+ int sku_id = get_kbl_sku();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sku_id < 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ return (sku_pl4_mapping[sku_id].pl4 + prop);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h</span><br><span>index 8073fcd..e68707d 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/cpu.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/cpu.h</span><br><span>@@ -57,4 +57,7 @@</span><br><span> u32 cpu_stepping(void);</span><br><span> int cpu_is_ult(void);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Calculate Psys Pmax value */</span><br><span style="color: hsl(120, 100%, 40%);">+u16 get_psys_pmax(u16 prop);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c</span><br><span>index 053e793..681a2e3 100644</span><br><span>--- a/src/soc/intel/skylake/vr_config.c</span><br><span>+++ b/src/soc/intel/skylake/vr_config.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "common.h"</span><br><span> #include <device/pci_ids.h></span><br><span> #include <fsp/api.h></span><br><span> #include <soc/ramstage.h></span><br><span>@@ -30,13 +31,6 @@</span><br><span> #define KBLU_ICCMAX_CORE_U22_BASE VR_CFG_AMP(29)</span><br><span> #define KBLUR_ICCMAX_GTS_GTUS VR_CFG_AMP(31)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-enum kbl_sku {</span><br><span style="color: hsl(0, 100%, 40%);">- KBL_Y_SKU,</span><br><span style="color: hsl(0, 100%, 40%);">- KBL_R_SKU,</span><br><span style="color: hsl(0, 100%, 40%);">- KBL_U_BASE_SKU,</span><br><span style="color: hsl(0, 100%, 40%);">- KBL_U_PREMIUM_SKU,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*</span><br><span> * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the</span><br><span> * Iccmax is the same among KBL-Y but KBL-U/R.</span><br><span>@@ -159,36 +153,6 @@</span><br><span> },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uint16_t get_dev_id(device_t dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return pci_read_config16(dev, PCI_DEVICE_ID);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int get_kbl_sku(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- static int sku = -1;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t id;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (sku != -1)</span><br><span style="color: hsl(0, 100%, 40%);">- return sku;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- id = get_dev_id(SA_DEV_ROOT);</span><br><span style="color: hsl(0, 100%, 40%);">- if (id == PCI_DEVICE_ID_INTEL_KBL_U_R)</span><br><span style="color: hsl(0, 100%, 40%);">- sku = KBL_R_SKU;</span><br><span style="color: hsl(0, 100%, 40%);">- else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y)</span><br><span style="color: hsl(0, 100%, 40%);">- sku = KBL_Y_SKU;</span><br><span style="color: hsl(0, 100%, 40%);">- else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) {</span><br><span style="color: hsl(0, 100%, 40%);">- id = get_dev_id(PCH_DEV_LPC);</span><br><span style="color: hsl(0, 100%, 40%);">- if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22)</span><br><span style="color: hsl(0, 100%, 40%);">- sku = KBL_U_BASE_SKU;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- sku = KBL_U_PREMIUM_SKU;</span><br><span style="color: hsl(0, 100%, 40%);">- } else</span><br><span style="color: hsl(0, 100%, 40%);">- /* Not one of the skus with available Icc max mapping. */</span><br><span style="color: hsl(0, 100%, 40%);">- sku = -2;</span><br><span style="color: hsl(0, 100%, 40%);">- return sku;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static uint16_t get_sku_icc_max(int domain, uint16_t board_icc_max)</span><br><span> {</span><br><span> /* If board provided non-zero value, use it. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23268">change 23268</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883 </div>
<div style="display:none"> Gerrit-Change-Number: 23268 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Gaggery Tsai <gaggery.tsai@intel.com> </div>