[coreboot-gerrit] Change in coreboot[master]: mainboard/google/zoombini: add EC to ACPI tables

[Caveh Jalali (Code Review)]

Hello caveh jalali,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/23237

to review the following change.


Change subject: mainboard/google/zoombini: add EC to ACPI tables
......................................................................

mainboard/google/zoombini: add EC to ACPI tables

this adds some missing ACPI entries for the EC and CPU.

BUG=b:71819257
BRANCH=chromeos-2016.05
TEST=booted on meowth.  /sys/class/power_supply now gets populated.

Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48
Signed-off-by: Caveh Jalali <caveh at chromium.org>
---
M src/mainboard/google/zoombini/dsdt.asl
M src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
2 files changed, 20 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/23237/1

diff --git a/src/mainboard/google/zoombini/dsdt.asl b/src/mainboard/google/zoombini/dsdt.asl
index c50a79a..25b74bf 100644
--- a/src/mainboard/google/zoombini/dsdt.asl
+++ b/src/mainboard/google/zoombini/dsdt.asl
@@ -15,6 +15,9 @@
  * GNU General Public License for more details.
  */
 
+#include "baseboard/ec.h"
+#include "baseboard/gpio.h"
+
 DefinitionBlock(
 	"dsdt.aml",
 	"DSDT",
@@ -30,7 +33,14 @@
 	// global NVS and variables
 	#include <soc/intel/cannonlake/acpi/globalnvs.asl>
 
+	// CPU
+	#include <soc/intel/cannonlake/acpi/cpu.asl>
+
 	Scope (\_SB) {
+		Device (PWRB)
+		{
+			Name (_HID, EisaId ("PNP0C0C"))
+		}
 		Device (PCI0)
 		{
 			#include <soc/intel/cannonlake/acpi/northbridge.asl>
@@ -45,4 +55,13 @@
 
 	// Chipset specific sleep states
 	#include <soc/intel/cannonlake/acpi/sleepstates.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
 }
diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
index e1b566d..ea48e62 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
@@ -32,7 +32,7 @@
 #define GPIO_PCH_WP		GPP_A1
 
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-#define GPE_EC_WAKE		GPP_74
+#define GPE_EC_WAKE		GPE0_LAN_WAK
 
 /* eSPI virtual wire reporting */
 #define EC_SCI_GPI		GPE0_ESPI

-- 
To view, visit https://review.coreboot.org/23237
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48
Gerrit-Change-Number: 23237
Gerrit-PatchSet: 1
Gerrit-Owner: Caveh Jalali <caveh at google.com>
Gerrit-Reviewer: caveh jalali <caveh at chromium.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180112/073b2148/attachment.html>