<p>Caveh Jalali would like caveh jalali to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/23237">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/zoombini: add EC to ACPI tables<br><br>this adds some missing ACPI entries for the EC and CPU.<br><br>BUG=b:71819257<br>BRANCH=chromeos-2016.05<br>TEST=booted on meowth.  /sys/class/power_supply now gets populated.<br><br>Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48<br>Signed-off-by: Caveh Jalali <caveh@chromium.org><br>---<br>M src/mainboard/google/zoombini/dsdt.asl<br>M src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h<br>2 files changed, 20 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/23237/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/dsdt.asl b/src/mainboard/google/zoombini/dsdt.asl</span><br><span>index c50a79a..25b74bf 100644</span><br><span>--- a/src/mainboard/google/zoombini/dsdt.asl</span><br><span>+++ b/src/mainboard/google/zoombini/dsdt.asl</span><br><span>@@ -15,6 +15,9 @@</span><br><span>  * GNU General Public License for more details.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include "baseboard/ec.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "baseboard/gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> DefinitionBlock(</span><br><span>    "dsdt.aml",</span><br><span>        "DSDT",</span><br><span>@@ -30,7 +33,14 @@</span><br><span>       // global NVS and variables</span><br><span>  #include <soc/intel/cannonlake/acpi/globalnvs.asl></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+  // CPU</span><br><span style="color: hsl(120, 100%, 40%);">+        #include <soc/intel/cannonlake/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+                Device (PWRB)</span><br><span style="color: hsl(120, 100%, 40%);">+         {</span><br><span style="color: hsl(120, 100%, 40%);">+                     Name (_HID, EisaId ("PNP0C0C"))</span><br><span style="color: hsl(120, 100%, 40%);">+             }</span><br><span>            Device (PCI0)</span><br><span>                {</span><br><span>                    #include <soc/intel/cannonlake/acpi/northbridge.asl></span><br><span>@@ -45,4 +55,13 @@</span><br><span> </span><br><span>  // Chipset specific sleep states</span><br><span>     #include <soc/intel/cannonlake/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+  /* Chrome OS Embedded Controller */</span><br><span style="color: hsl(120, 100%, 40%);">+   Scope (\_SB.PCI0.LPCB)</span><br><span style="color: hsl(120, 100%, 40%);">+        {</span><br><span style="color: hsl(120, 100%, 40%);">+             /* ACPI code for EC SuperIO functions */</span><br><span style="color: hsl(120, 100%, 40%);">+              #include <ec/google/chromeec/acpi/superio.asl></span><br><span style="color: hsl(120, 100%, 40%);">+          /* ACPI code for EC functions */</span><br><span style="color: hsl(120, 100%, 40%);">+              #include <ec/google/chromeec/acpi/ec.asl></span><br><span style="color: hsl(120, 100%, 40%);">+       }</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h</span><br><span>index e1b566d..ea48e62 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h</span><br><span>+++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h</span><br><span>@@ -32,7 +32,7 @@</span><br><span> #define GPIO_PCH_WP              GPP_A1</span><br><span> </span><br><span> /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPE_EC_WAKE          GPP_74</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_EC_WAKE             GPE0_LAN_WAK</span><br><span> </span><br><span> /* eSPI virtual wire reporting */</span><br><span> #define EC_SCI_GPI             GPE0_ESPI</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23237">change 23237</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23237"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48 </div>
<div style="display:none"> Gerrit-Change-Number: 23237 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Caveh Jalali <caveh@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: caveh jalali <caveh@chromium.org> </div>