[coreboot-gerrit] Change in coreboot[master]: mainboard/google/kahlee: Enable PCIe Lane 2
Martin Roth (Code Review)
gerrit at coreboot.org
Thu Jan 11 01:57:58 CET 2018
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/23210
Change subject: mainboard/google/kahlee: Enable PCIe Lane 2
......................................................................
mainboard/google/kahlee: Enable PCIe Lane 2
The Port initializer had been changed from PortDisabled to PortEnabled,
but engine inializer hadn't been updated from PciePortEngine to
PciePortEngine. Update this so the port works.
BUG=b:71818026
TEST=PCIe device now shows up on D2F4
Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7
---
M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/23210/1
diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
index 622152b..aa0edf7 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
@@ -52,7 +52,7 @@
/* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2(
PortDisabled, /* mPortPresent */
ChannelTypeExt6db, /* mChannelType */
@@ -68,7 +68,7 @@
/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2(
PortEnabled, /* mPortPresent */
ChannelTypeExt6db, /* mChannelType */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7
Gerrit-Change-Number: 23210
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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