<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23210">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/kahlee: Enable PCIe Lane 2<br><br>The Port initializer had been changed from PortDisabled to PortEnabled,<br>but engine inializer hadn't been updated from PciePortEngine to<br>PciePortEngine.  Update this so the port works.<br><br>BUG=b:71818026<br>TEST=PCIe device now shows up on D2F4<br><br>Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7<br>---<br>M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c<br>1 file changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/23210/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c</span><br><span>index 622152b..aa0edf7 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c</span><br><span>@@ -52,7 +52,7 @@</span><br><span>        /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */</span><br><span>   {</span><br><span>            0,</span><br><span style="color: hsl(0, 100%, 40%);">-              PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+           PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),</span><br><span>                PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span>                               PortDisabled,           /* mPortPresent */</span><br><span>                           ChannelTypeExt6db,      /* mChannelType */</span><br><span>@@ -68,7 +68,7 @@</span><br><span>       /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */</span><br><span>  {</span><br><span>            0,</span><br><span style="color: hsl(0, 100%, 40%);">-              PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),</span><br><span style="color: hsl(120, 100%, 40%);">+         PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),</span><br><span>          PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span>                               PortEnabled,            /* mPortPresent */</span><br><span>                           ChannelTypeExt6db,      /* mChannelType */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23210">change 23210</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23210"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7 </div>
<div style="display:none"> Gerrit-Change-Number: 23210 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>