[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Keep SPI flash cacheable during POST

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23205


Change subject: amd/stoneyridge: Keep SPI flash cacheable during POST
......................................................................

amd/stoneyridge: Keep SPI flash cacheable during POST

A side effect of using the common MTRR assignment code is the flash
device loses its WP setting and is no longer cacheable.  After MTRR
setup, reenable the setting for the duration of POST.

TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate()
BUG=b:70536683

Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/cpu.c
1 file changed, 5 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/23205/1

diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 0490137..86429e2 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -24,6 +24,7 @@
 #include <soc/cpu.h>
 #include <soc/northbridge.h>
 #include <soc/smi.h>
+#include <soc/iomap.h>
 #include <console/console.h>
 
 /*
@@ -47,6 +48,10 @@
 static void pre_mp_init(void)
 {
 	x86_setup_mtrrs_with_detect();
+
+	/* The flash is now no longer cacheable. Reset to WP for performance. */
+	mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
 	x86_mtrr_check();
 }
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730
Gerrit-Change-Number: 23205
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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