<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23205">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Keep SPI flash cacheable during POST<br><br>A side effect of using the common MTRR assignment code is the flash<br>device loses its WP setting and is no longer cacheable.  After MTRR<br>setup, reenable the setting for the duration of POST.<br><br>TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate()<br>BUG=b:70536683<br><br>Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/cpu.c<br>1 file changed, 5 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/23205/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c</span><br><span>index 0490137..86429e2 100644</span><br><span>--- a/src/soc/amd/stoneyridge/cpu.c</span><br><span>+++ b/src/soc/amd/stoneyridge/cpu.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/northbridge.h></span><br><span> #include <soc/smi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span> #include <console/console.h></span><br><span> </span><br><span> /*</span><br><span>@@ -47,6 +48,10 @@</span><br><span> static void pre_mp_init(void)</span><br><span> {</span><br><span>   x86_setup_mtrrs_with_detect();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+      /* The flash is now no longer cacheable. Reset to WP for performance. */</span><br><span style="color: hsl(120, 100%, 40%);">+      mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>   x86_mtrr_check();</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23205">change 23205</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23205"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730 </div>
<div style="display:none"> Gerrit-Change-Number: 23205 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>