[coreboot-gerrit] Change in coreboot[master]: mainboard/google/zoombini: enable USB and assign acpi irq

[Nick Vaccaro (Code Review)]

Hello Nick Vaccaro,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/23191

to review the following change.


Change subject: mainboard/google/zoombini: enable USB and assign acpi irq
......................................................................

mainboard/google/zoombini: enable USB and assign acpi irq

-add USB2 and USB3 to devicetree
-add TPM_TIS_ACPI_INTERRUPT to Kconfig
-map gpe0_dw0, gpe0_dw1, and gpe0_dw2 blocks

BUG=b:64395641
BRANCH=chromeos-2016.05
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.

Change-Id: Ia7ed76591d9d8d94bbf5652313c478495ce005fa
Signed-off-by: Nick Vaccaro <nvaccaro at chromium.org>
---
M src/mainboard/google/zoombini/Kconfig
M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
2 files changed, 46 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/23191/1

diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig
index 2fe8fec..8e1cfbb 100644
--- a/src/mainboard/google/zoombini/Kconfig
+++ b/src/mainboard/google/zoombini/Kconfig
@@ -86,4 +86,8 @@
 	select SPI_TPM
 	select TPM2
 
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 76 # GPE0_DW2_12 (GPP_C12)
+
 endif # BOARD_GOOGLE_BASEBOARD_ZOOMBINI
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
index 771bab2..bb9cb9a 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
@@ -1,9 +1,51 @@
 chip soc/intel/cannonlake
 
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# GPP_C is "8"
+	register "gpe0_dw0" = "PMC_GPP_A"
+	register "gpe0_dw1" = "PMC_GPP_B"
+	register "gpe0_dw2" = "PMC_GPP_C"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end
 
+	# FSP configuration
+	register "SaGv" = "3"
+	register "FspSkipMpInit" = "1"
+	register "SmbusEnable" = "1"
+	register "ScsEmmcEnabled" = "1"
+	register "ScsEmmcHs400Enabled" = "1"
+	register "ScsSdCardEnabled" = "1"
+
+	# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
+	# communication before memory is up.
+	register "gspi[0]" = "{
+		.speed_mhz = 1,
+		.early_init = 1,
+	}"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+	register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+	register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+	register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+	register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia7ed76591d9d8d94bbf5652313c478495ce005fa
Gerrit-Change-Number: 23191
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro at chromium.org>
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