<p>Nick Vaccaro would like Nick Vaccaro to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/23191">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/zoombini: enable USB and assign acpi irq<br><br>-add USB2 and USB3 to devicetree<br>-add TPM_TIS_ACPI_INTERRUPT to Kconfig<br>-map gpe0_dw0, gpe0_dw1, and gpe0_dw2 blocks<br><br>BUG=b:64395641<br>BRANCH=chromeos-2016.05<br>TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"<br>compiles successfully.<br><br>Change-Id: Ia7ed76591d9d8d94bbf5652313c478495ce005fa<br>Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org><br>---<br>M src/mainboard/google/zoombini/Kconfig<br>M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>2 files changed, 46 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/23191/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig</span><br><span>index 2fe8fec..8e1cfbb 100644</span><br><span>--- a/src/mainboard/google/zoombini/Kconfig</span><br><span>+++ b/src/mainboard/google/zoombini/Kconfig</span><br><span>@@ -86,4 +86,8 @@</span><br><span> select SPI_TPM</span><br><span> select TPM2</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config TPM_TIS_ACPI_INTERRUPT</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 76 # GPE0_DW2_12 (GPP_C12)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif # BOARD_GOOGLE_BASEBOARD_ZOOMBINI</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>index 771bab2..bb9cb9a 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>@@ -1,9 +1,51 @@</span><br><span> chip soc/intel/cannonlake</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPP_C is "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "PMC_GPP_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "PMC_GPP_C"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device cpu_cluster 0 on</span><br><span> device lapic 0 on end</span><br><span> end</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsSdCardEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ # communication before memory is up.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gspi[0]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_mhz = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device domain 0 on</span><br><span> device pci 00.0 on end # Host Bridge</span><br><span> device pci 02.0 on end # Integrated Graphics Device</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23191">change 23191</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia7ed76591d9d8d94bbf5652313c478495ce005fa </div>
<div style="display:none"> Gerrit-Change-Number: 23191 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Nick Vaccaro <nvaccaro@chromium.org> </div>