[coreboot-gerrit] Change in coreboot[master]: [NOTFORMERGE, TEST] nb/intel/i945: Use postcar stage to tear down CAR
Arthur Heymans (Code Review)
gerrit at coreboot.org
Tue Jan 9 15:33:06 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23184
Change subject: [NOTFORMERGE,TEST] nb/intel/i945: Use postcar stage to tear down CAR
......................................................................
[NOTFORMERGE,TEST] nb/intel/i945: Use postcar stage to tear down CAR
This is a mere hack, clean it up!
Change-Id: I4f41379cbb2ac251c97682d33ae8ee3729d1d567
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/car/romstage.c
M src/cpu/intel/model_6ex/Makefile.inc
M src/cpu/intel/model_6ex/cache_as_ram.inc
M src/mainboard/lenovo/x60/romstage.c
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/Makefile.inc
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/ram_calc.c
8 files changed, 50 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/23184/1
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 555c384..a25dc6d 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -23,7 +23,7 @@
asmlinkage void *romstage_main(unsigned long bist)
{
int i;
- void *romstage_stack_after_car;
+// void *romstage_stack_after_car;
const int num_guards = 4;
const u32 stack_guard = 0xdeadbeef;
u32 *stack_base;
@@ -53,9 +53,11 @@
}
/* Get the stack to use after cache-as-ram is torn down. */
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
romstage_stack_after_car = setup_stack_and_mtrrs();
-
return romstage_stack_after_car;
+#endif
+ return NULL;
}
asmlinkage void romstage_after_car(void)
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 4321f2a..e2114a0 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -3,3 +3,5 @@
subdirs-y += ../common
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
+
+postcar-$(CONFIG_POSTCAR_STAGE) += teardown_car.S
\ No newline at end of file
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 4b85c07..20ca472 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -138,6 +138,11 @@
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
+
+#if IS_ENABLED(CONFIG_POSTCAR_STAGE)
+ jmp postcar_entry_failure
+#endif
+
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
@@ -253,6 +258,11 @@
hlt
jmp .Lhlt
+postcar_entry_failure:
+ /* Should never see this postcode */
+ post_code(0xae)
+ jmp .Lhlt
+
mtrr_table:
/* Fixed MTRRs */
.word 0x250, 0x258, 0x259
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index eddb150..d5d8d01 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -38,6 +38,8 @@
#include <southbridge/intel/common/gpio.h>
#include "dock.h"
+static int test = 0;
+
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
@@ -62,6 +64,7 @@
static void early_superio_config(void)
{
+ test = 1;
int timeout = 100000;
pnp_devfn_t dev = PNP_DEV(0x2e, 3);
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 482f98a..ddbba94 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -28,6 +28,7 @@
select RELOCATABLE_RAMSTAGE
select INTEL_EDID
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+ select POSTCAR_STAGE
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 0e4fcfc..ffeabdc 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -29,4 +29,6 @@
smm-y += udelay.c
+postcar-y += ram_calc.c
+
endif
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index bf486a0..9eefa76 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <assert.h>
#include <stdint.h>
#include <stdlib.h>
#include <console/console.h>
@@ -26,6 +27,7 @@
#include "i945.h"
#include <pc80/mc146818rtc.h>
#include <southbridge/intel/common/gpio.h>
+#include <cpu/x86/mtrr.h>
int i945_silicon_revision(void)
{
@@ -929,8 +931,13 @@
romstage_handoff_init(cbmem_was_initted && s3resume);
}
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
void i945_late_initialization(int s3resume)
{
+ u32 top_of_ram;
+ struct postcar_frame pcf;
+
i945_setup_egress_port();
ich7_setup_root_complex_topology();
@@ -966,4 +973,25 @@
MCHBAR16(SSKPD) = 0xCAFE;
i945_prepare_resume(s3resume);
+
+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ die("Unable to initialize postcar frame.\n");
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+ /* Cache two separate 4 MiB regions below the top of ram, this
+ * satisfies MTRR alignment requirements. If you modify this to
+ * cover TSEG, make sure UMA region is not set with WRBACK as it
+ * causes hard-to-recover boot failures.
+ */
+ top_of_ram = (uintptr_t)cbmem_top();
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+
+ run_postcar_phase(&pcf);
}
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 0c337bb..80ab603 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -77,37 +77,3 @@
return ggc2uma[gms] << 10;
}
-
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
-/* setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mtrrs(void)
-{
- struct postcar_frame pcf;
- uintptr_t top_of_ram;
-
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
- die("Unable to initialize postcar frame.\n");
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
- MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
- /* Cache two separate 4 MiB regions below the top of ram, this
- * satisfies MTRR alignment requirements. If you modify this to
- * cover TSEG, make sure UMA region is not set with WRBACK as it
- * causes hard-to-recover boot failures.
- */
- top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
-
- /* Save the number of MTRRs to setup. Return the stack location
- * pointing to the number of MTRRs.
- */
- return postcar_commit_mtrrs(&pcf);
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4f41379cbb2ac251c97682d33ae8ee3729d1d567
Gerrit-Change-Number: 23184
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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