<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23184">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[NOTFORMERGE,TEST] nb/intel/i945: Use postcar stage to tear down CAR<br><br>This is a mere hack, clean it up!<br><br>Change-Id: I4f41379cbb2ac251c97682d33ae8ee3729d1d567<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/car/romstage.c<br>M src/cpu/intel/model_6ex/Makefile.inc<br>M src/cpu/intel/model_6ex/cache_as_ram.inc<br>M src/mainboard/lenovo/x60/romstage.c<br>M src/northbridge/intel/i945/Kconfig<br>M src/northbridge/intel/i945/Makefile.inc<br>M src/northbridge/intel/i945/early_init.c<br>M src/northbridge/intel/i945/ram_calc.c<br>8 files changed, 50 insertions(+), 36 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/23184/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c</span><br><span>index 555c384..a25dc6d 100644</span><br><span>--- a/src/cpu/intel/car/romstage.c</span><br><span>+++ b/src/cpu/intel/car/romstage.c</span><br><span>@@ -23,7 +23,7 @@</span><br><span> asmlinkage void *romstage_main(unsigned long bist)</span><br><span> {</span><br><span> int i;</span><br><span style="color: hsl(0, 100%, 40%);">- void *romstage_stack_after_car;</span><br><span style="color: hsl(120, 100%, 40%);">+// void *romstage_stack_after_car;</span><br><span> const int num_guards = 4;</span><br><span> const u32 stack_guard = 0xdeadbeef;</span><br><span> u32 *stack_base;</span><br><span>@@ -53,9 +53,11 @@</span><br><span> }</span><br><span> </span><br><span> /* Get the stack to use after cache-as-ram is torn down. */</span><br><span style="color: hsl(120, 100%, 40%);">+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)</span><br><span> romstage_stack_after_car = setup_stack_and_mtrrs();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> return romstage_stack_after_car;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span> }</span><br><span> </span><br><span> asmlinkage void romstage_after_car(void)</span><br><span>diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc</span><br><span>index 4321f2a..e2114a0 100644</span><br><span>--- a/src/cpu/intel/model_6ex/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_6ex/Makefile.inc</span><br><span>@@ -3,3 +3,5 @@</span><br><span> subdirs-y += ../common</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_POSTCAR_STAGE) += teardown_car.S</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span>index 4b85c07..20ca472 100644</span><br><span>--- a/src/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span>+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span>@@ -138,6 +138,11 @@</span><br><span> post_code(0x29)</span><br><span> /* Call romstage.c main function. */</span><br><span> call romstage_main</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_POSTCAR_STAGE)</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp postcar_entry_failure</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Save return value from romstage_main. It contains the stack to use</span><br><span> * after cache-as-ram is torn down. It also contains the information</span><br><span> * for setting up MTRRs. */</span><br><span>@@ -253,6 +258,11 @@</span><br><span> hlt</span><br><span> jmp .Lhlt</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar_entry_failure:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Should never see this postcode */</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0xae)</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .Lhlt</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> mtrr_table:</span><br><span> /* Fixed MTRRs */</span><br><span> .word 0x250, 0x258, 0x259</span><br><span>diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c</span><br><span>index eddb150..d5d8d01 100644</span><br><span>--- a/src/mainboard/lenovo/x60/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x60/romstage.c</span><br><span>@@ -38,6 +38,8 @@</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include "dock.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static int test = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> // Enable Serial IRQ</span><br><span>@@ -62,6 +64,7 @@</span><br><span> </span><br><span> static void early_superio_config(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ test = 1;</span><br><span> int timeout = 100000;</span><br><span> pnp_devfn_t dev = PNP_DEV(0x2e, 3);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig</span><br><span>index 482f98a..ddbba94 100644</span><br><span>--- a/src/northbridge/intel/i945/Kconfig</span><br><span>+++ b/src/northbridge/intel/i945/Kconfig</span><br><span>@@ -28,6 +28,7 @@</span><br><span> select RELOCATABLE_RAMSTAGE</span><br><span> select INTEL_EDID</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span> </span><br><span> config NORTHBRIDGE_INTEL_SUBTYPE_I945GC</span><br><span> def_bool n</span><br><span>diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc</span><br><span>index 0e4fcfc..ffeabdc 100644</span><br><span>--- a/src/northbridge/intel/i945/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/i945/Makefile.inc</span><br><span>@@ -29,4 +29,6 @@</span><br><span> </span><br><span> smm-y += udelay.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c</span><br><span>index bf486a0..9eefa76 100644</span><br><span>--- a/src/northbridge/intel/i945/early_init.c</span><br><span>+++ b/src/northbridge/intel/i945/early_init.c</span><br><span>@@ -13,6 +13,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span> #include <stdint.h></span><br><span> #include <stdlib.h></span><br><span> #include <console/console.h></span><br><span>@@ -26,6 +27,7 @@</span><br><span> #include "i945.h"</span><br><span> #include <pc80/mc146818rtc.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span> </span><br><span> int i945_silicon_revision(void)</span><br><span> {</span><br><span>@@ -929,8 +931,13 @@</span><br><span> romstage_handoff_init(cbmem_was_initted && s3resume);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void i945_late_initialization(int s3resume)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 top_of_ram;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct postcar_frame pcf;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> i945_setup_egress_port();</span><br><span> </span><br><span> ich7_setup_root_complex_topology();</span><br><span>@@ -966,4 +973,25 @@</span><br><span> MCHBAR16(SSKPD) = 0xCAFE;</span><br><span> </span><br><span> i945_prepare_resume(s3resume);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Unable to initialize postcar frame.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache two separate 4 MiB regions below the top of ram, this</span><br><span style="color: hsl(120, 100%, 40%);">+ * satisfies MTRR alignment requirements. If you modify this to</span><br><span style="color: hsl(120, 100%, 40%);">+ * cover TSEG, make sure UMA region is not set with WRBACK as it</span><br><span style="color: hsl(120, 100%, 40%);">+ * causes hard-to-recover boot failures.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ top_of_ram = (uintptr_t)cbmem_top();</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span> }</span><br><span>diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c</span><br><span>index 0c337bb..80ab603 100644</span><br><span>--- a/src/northbridge/intel/i945/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/i945/ram_calc.c</span><br><span>@@ -77,37 +77,3 @@</span><br><span> </span><br><span> return ggc2uma[gms] << 10;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* setup_stack_and_mtrrs() determines the stack to use after</span><br><span style="color: hsl(0, 100%, 40%);">- * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span style="color: hsl(0, 100%, 40%);">-void *setup_stack_and_mtrrs(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct postcar_frame pcf;</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t top_of_ram;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(0, 100%, 40%);">- die("Unable to initialize postcar frame.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache two separate 4 MiB regions below the top of ram, this</span><br><span style="color: hsl(0, 100%, 40%);">- * satisfies MTRR alignment requirements. If you modify this to</span><br><span style="color: hsl(0, 100%, 40%);">- * cover TSEG, make sure UMA region is not set with WRBACK as it</span><br><span style="color: hsl(0, 100%, 40%);">- * causes hard-to-recover boot failures.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- top_of_ram = (uintptr_t)cbmem_top();</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">- * pointing to the number of MTRRs.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23184">change 23184</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23184"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4f41379cbb2ac251c97682d33ae8ee3729d1d567 </div>
<div style="display:none"> Gerrit-Change-Number: 23184 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>