[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/skylake: Add gpio groups

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/23179


Change subject: src/soc/intel/skylake: Add gpio groups
......................................................................

src/soc/intel/skylake: Add gpio groups

Add the information about groups within each community.

Change-Id: If69373a70277f9f9d62763a6c852161e2a2f48f3
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/soc/intel/skylake/gpio.c
1 file changed, 46 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/23179/1

diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 9c9d041..99ccf6d 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -20,6 +20,12 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
+#define SKL_GPP(s, e)				\
+	{						\
+		.first_pad = (s),			\
+		.size = ((e) - (s) + 1),		\
+	}
+
 static const struct reset_mapping rst_map[] = {
 	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30},
 	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30},
@@ -33,6 +39,38 @@
 	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30},
 };
 
+static const struct pad_group skl_community_com0_groups[] = {
+	SKL_GPP(GPP_A0, GPP_A23),	/* GPP A */
+	SKL_GPP(GPP_B0, GPP_B23),	/* GPP B */
+};
+
+static const struct pad_group skl_community_com1_groups[] = {
+	SKL_GPP(GPP_C0, GPP_C23),	/* GPP C */
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+	SKL_GPP(GPP_D0, GPP_D23),	/* GPP D */
+	SKL_GPP(GPP_E0, GPP_E12),	/* GPP E */
+	SKL_GPP(GPP_F0, GPP_F23),	/* GPP F */
+	SKL_GPP(GPP_G0, GPP_G23),	/* GPP G */
+	SKL_GPP(GPP_H0, GPP_H23),	/* GPP H */
+#else
+	SKL_GPP(GPP_D0, GPP_D23),	/* GPP D */
+	SKL_GPP(GPP_E0, GPP_E23),	/* GPP E */
+#endif
+};
+
+static const struct pad_group skl_community_com3_groups[] = {
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+	SKL_GPP(GPP_I0, GPP_I10),	/* GPP I */
+#else
+	SKL_GPP(GPP_F0, GPP_F23),	/* GPP F */
+	SKL_GPP(GPP_G0, GPP_G7),	/* GPP G */
+#endif
+};
+
+static const struct pad_group skl_community_com2_groups[] = {
+	SKL_GPP(GPD0, GPD11),		/* GPP GDP */
+};
+
 static const struct pad_community skl_gpio_communities[] = {
 	{
 		.port = PID_GPIOCOM0,
@@ -48,6 +86,8 @@
 		.acpi_path = "\\_SB.PCI0.GPIO",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = skl_community_com0_groups,
+		.num_groups = ARRAY_SIZE(skl_community_com0_groups),
 	}, {
 		.port = PID_GPIOCOM1,
 		.first_pad = GPP_C0,
@@ -66,6 +106,8 @@
 		.acpi_path = "\\_SB.PCI0.GPIO",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = skl_community_com1_groups,
+		.num_groups = ARRAY_SIZE(skl_community_com1_groups),
 	}, {
 		.port = PID_GPIOCOM3,
 #if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
@@ -85,6 +127,8 @@
 		.acpi_path = "\\_SB.PCI0.GPIO",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = skl_community_com3_groups,
+		.num_groups = ARRAY_SIZE(skl_community_com3_groups),
 	}, {
 		.port = PID_GPIOCOM2,
 		.first_pad = GPD0,
@@ -99,6 +143,8 @@
 		.acpi_path = "\\_SB.PCI0.GPIO",
 		.reset_map = rst_map_com2,
 		.num_reset_vals = ARRAY_SIZE(rst_map_com2),
+		.groups = skl_community_com2_groups,
+		.num_groups = ARRAY_SIZE(skl_community_com2_groups),
 	}
 };
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If69373a70277f9f9d62763a6c852161e2a2f48f3
Gerrit-Change-Number: 23179
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
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