[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Remove redundent CNL CPUID macros

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23159


Change subject: soc/intel/cannonlake: Remove redundent CNL CPUID macros
......................................................................

soc/intel/cannonlake: Remove redundent CNL CPUID macros

This patch ensures all CannonLake CPUIDs are part of mp_init.h
hence remove duplicate macro definitios from SoC code.

TEST=Build and boot CannonLake RVP

Change-Id: Ibb6a22d5c708248bb53522f906cffb462142b7bf
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/include/soc/cpu.h
2 files changed, 3 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/23159/1

diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index 9bca7ac..969a8f7 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,8 +20,8 @@
 #include <cpu/x86/msr.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <intelblocks/mp_init.h>
 #include <soc/bootblock.h>
-#include <soc/cpu.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <string.h>
diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h
index e50801f..bde8f28 100644
--- a/src/soc/intel/cannonlake/include/soc/cpu.h
+++ b/src/soc/intel/cannonlake/include/soc/cpu.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,12 +21,6 @@
 #include <device/device.h>
 #include <intelblocks/msr.h>
 
-/* Supported CPUIDs */
-#define CPUID_CANNONLAKE_A0	0x60660
-#define CPUID_CANNONLAKE_B0	0x60661
-#define CPUID_CANNONLAKE_C0	0x60662
-#define CPUID_CANNONLAKE_D0	0x60663
-
 /* Latency times in units of 1024ns. */
 #define C_STATE_LATENCY_CONTROL_0_LIMIT	0x4e
 #define C_STATE_LATENCY_CONTROL_1_LIMIT	0x76

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibb6a22d5c708248bb53522f906cffb462142b7bf
Gerrit-Change-Number: 23159
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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