<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23159">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Remove redundent CNL CPUID macros<br><br>This patch ensures all CannonLake CPUIDs are part of mp_init.h<br>hence remove duplicate macro definitios from SoC code.<br><br>TEST=Build and boot CannonLake RVP<br><br>Change-Id: Ibb6a22d5c708248bb53522f906cffb462142b7bf<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/bootblock/report_platform.c<br>M src/soc/intel/cannonlake/include/soc/cpu.h<br>2 files changed, 3 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/23159/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>index 9bca7ac..969a8f7 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>@@ -2,7 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015-2018 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -20,8 +20,8 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_init.h></span><br><span> #include <soc/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cpu.h></span><br><span> #include <soc/pch.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <string.h></span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h</span><br><span>index e50801f..bde8f28 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/cpu.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/cpu.h</span><br><span>@@ -2,7 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -21,12 +21,6 @@</span><br><span> #include <device/device.h></span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Supported CPUIDs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_CANNONLAKE_A0 0x60660</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_CANNONLAKE_B0 0x60661</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_CANNONLAKE_C0 0x60662</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_CANNONLAKE_D0 0x60663</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Latency times in units of 1024ns. */</span><br><span> #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e</span><br><span> #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23159">change 23159</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23159"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibb6a22d5c708248bb53522f906cffb462142b7bf </div>
<div style="display:none"> Gerrit-Change-Number: 23159 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>