[coreboot-gerrit] Change in coreboot[master]: [TESTONLY] Use common mrc_cache on Thinkpad x200

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23147


Change subject: [TESTONLY] Use common mrc_cache on Thinkpad x200
......................................................................

[TESTONLY] Use common mrc_cache on Thinkpad x200

NOTFORMERGE.

Change-Id: I67fdb3fd1557e68bb2ed2b135c0b3a6a13783605
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/lenovo/x200/romstage.c
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/raminit.c
M src/southbridge/intel/i82801ix/Kconfig
4 files changed, 34 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/23147/1

diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index d8ed039..bdb9252 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -33,6 +33,7 @@
 #include <northbridge/intel/gm45/gm45.h>
 #include "gpio.h"
 #include <timestamp.h>
+#include <mrc_cache.h>
 
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
 #define MCH_DEV PCI_DEV(0, 0, 0)
@@ -162,6 +163,8 @@
 	outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
 
 	cbmem_initted = !cbmem_recovery(s3resume);
+	mrc_cache_stash_data(MRC_TRAINING_DATA, 1, &sysinfo,
+			sizeof(sysinfo));
 
 	romstage_handoff_init(cbmem_initted && s3resume);
 
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 85902d3..7e1e0e6 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -29,6 +29,7 @@
 	select RELOCATABLE_RAMSTAGE
 	select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+	select CACHE_MRC_SETTINGS
 
 config CBFS_SIZE
 	hex
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index a44e397..9895590 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
 #include <arch/cpu.h>
@@ -26,9 +27,14 @@
 #include <lib.h>
 #include <delay.h>
 #include <timestamp.h>
+#include <commonlib/region.h>
+#include <mrc_cache.h>
+#include <halt.h>
 #include "gm45.h"
 #include "chip.h"
 
+#define MRC_CACHE_VERSION 1
+
 static const gmch_gfx_t gmch_gfx_types[][5] = {
 /*  MAX_667MHz    MAX_533MHz    MAX_400MHz    MAX_333MHz    MAX_800MHz    */
   { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN  },
@@ -1706,12 +1712,31 @@
 {
 	const dimminfo_t *const dimms = sysinfo->dimms;
 	const timings_t *const timings = &sysinfo->selected_timings;
+	struct region_device rdev;
+	sysinfo_t *ctrl_cached;
 
 	int ch;
 	u8 reg8;
 
 	timestamp_add_now(TS_BEFORE_INITRAM);
 
+	int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA,
+						MRC_CACHE_VERSION, &rdev);
+	if (cache_not_found || (region_device_sz(&rdev) < sizeof(*sysinfo))) {
+		if (s3resume) {
+			/* Failed S3 resume, reset to come up cleanly */
+			outb(0x6, 0xcf9);
+			halt();
+		}
+		ctrl_cached = NULL;
+	} else {
+		ctrl_cached = rdev_mmap_full(&rdev);
+	}
+
+	if (ctrl_cached) {
+		memcpy(sysinfo, ctrl_cached, sizeof(*sysinfo));
+	}
+
 	/* Wait for some bit, maybe TXT clear. */
 	if (sysinfo->txt_enabled) {
 		while (!(read8((u8 *)0xfed40000) & (1 << 7))) {}
@@ -1824,5 +1849,8 @@
 	raminit_thermal(sysinfo);
 	init_igd(sysinfo);
 
+	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, sysinfo,
+			sizeof(*sysinfo));
+
 	timestamp_add_now(TS_AFTER_INITRAM);
 }
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 6879bce..333de7f 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -18,6 +18,7 @@
 	bool
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+	select SOUTHBRIDGE_INTEL_COMMON_SPI
 	select IOAPIC
 	select HAVE_USBDEBUG
 	select HAVE_HARD_RESET
@@ -25,7 +26,7 @@
 	select HAVE_SMI_HANDLER
 	select HAVE_USBDEBUG_OPTIONS
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
-	select HAVE_INTEL_FIRMWARE
+	select HAVE_INTEL_FIRMWARE if !BOARD_EMULATION_QEMU_X86_Q35
 
 if SOUTHBRIDGE_INTEL_I82801IX
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I67fdb3fd1557e68bb2ed2b135c0b3a6a13783605
Gerrit-Change-Number: 23147
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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