<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23147">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[TESTONLY] Use common mrc_cache on Thinkpad x200<br><br>NOTFORMERGE.<br><br>Change-Id: I67fdb3fd1557e68bb2ed2b135c0b3a6a13783605<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/lenovo/x200/romstage.c<br>M src/northbridge/intel/gm45/Kconfig<br>M src/northbridge/intel/gm45/raminit.c<br>M src/southbridge/intel/i82801ix/Kconfig<br>4 files changed, 34 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/23147/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c</span><br><span>index d8ed039..bdb9252 100644</span><br><span>--- a/src/mainboard/lenovo/x200/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x200/romstage.c</span><br><span>@@ -33,6 +33,7 @@</span><br><span> #include <northbridge/intel/gm45/gm45.h></span><br><span> #include "gpio.h"</span><br><span> #include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <mrc_cache.h></span><br><span> </span><br><span> #define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define MCH_DEV PCI_DEV(0, 0, 0)</span><br><span>@@ -162,6 +163,8 @@</span><br><span> outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);</span><br><span> </span><br><span> cbmem_initted = !cbmem_recovery(s3resume);</span><br><span style="color: hsl(120, 100%, 40%);">+ mrc_cache_stash_data(MRC_TRAINING_DATA, 1, &sysinfo,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(sysinfo));</span><br><span> </span><br><span> romstage_handoff_init(cbmem_initted && s3resume);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig</span><br><span>index 85902d3..7e1e0e6 100644</span><br><span>--- a/src/northbridge/intel/gm45/Kconfig</span><br><span>+++ b/src/northbridge/intel/gm45/Kconfig</span><br><span>@@ -29,6 +29,7 @@</span><br><span> select RELOCATABLE_RAMSTAGE</span><br><span> select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select CACHE_MRC_SETTINGS</span><br><span> </span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span>diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c</span><br><span>index a44e397..9895590 100644</span><br><span>--- a/src/northbridge/intel/gm45/raminit.c</span><br><span>+++ b/src/northbridge/intel/gm45/raminit.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span> #include <stdint.h></span><br><span> #include <stdlib.h></span><br><span> #include <arch/cpu.h></span><br><span>@@ -26,9 +27,14 @@</span><br><span> #include <lib.h></span><br><span> #include <delay.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/region.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <mrc_cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <halt.h></span><br><span> #include "gm45.h"</span><br><span> #include "chip.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_CACHE_VERSION 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static const gmch_gfx_t gmch_gfx_types[][5] = {</span><br><span> /* MAX_667MHz MAX_533MHz MAX_400MHz MAX_333MHz MAX_800MHz */</span><br><span> { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN },</span><br><span>@@ -1706,12 +1712,31 @@</span><br><span> {</span><br><span> const dimminfo_t *const dimms = sysinfo->dimms;</span><br><span> const timings_t *const timings = &sysinfo->selected_timings;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct region_device rdev;</span><br><span style="color: hsl(120, 100%, 40%);">+ sysinfo_t *ctrl_cached;</span><br><span> </span><br><span> int ch;</span><br><span> u8 reg8;</span><br><span> </span><br><span> timestamp_add_now(TS_BEFORE_INITRAM);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_CACHE_VERSION, &rdev);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cache_not_found || (region_device_sz(&rdev) < sizeof(*sysinfo))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s3resume) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Failed S3 resume, reset to come up cleanly */</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x6, 0xcf9);</span><br><span style="color: hsl(120, 100%, 40%);">+ halt();</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl_cached = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl_cached = rdev_mmap_full(&rdev);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ctrl_cached) {</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(sysinfo, ctrl_cached, sizeof(*sysinfo));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Wait for some bit, maybe TXT clear. */</span><br><span> if (sysinfo->txt_enabled) {</span><br><span> while (!(read8((u8 *)0xfed40000) & (1 << 7))) {}</span><br><span>@@ -1824,5 +1849,8 @@</span><br><span> raminit_thermal(sysinfo);</span><br><span> init_igd(sysinfo);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, sysinfo,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(*sysinfo));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> timestamp_add_now(TS_AFTER_INITRAM);</span><br><span> }</span><br><span>diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig</span><br><span>index 6879bce..333de7f 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/Kconfig</span><br><span>+++ b/src/southbridge/intel/i82801ix/Kconfig</span><br><span>@@ -18,6 +18,7 @@</span><br><span> bool</span><br><span> select SOUTHBRIDGE_INTEL_COMMON</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_COMMON_SPI</span><br><span> select IOAPIC</span><br><span> select HAVE_USBDEBUG</span><br><span> select HAVE_HARD_RESET</span><br><span>@@ -25,7 +26,7 @@</span><br><span> select HAVE_SMI_HANDLER</span><br><span> select HAVE_USBDEBUG_OPTIONS</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_GPIO</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_INTEL_FIRMWARE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_INTEL_FIRMWARE if !BOARD_EMULATION_QEMU_X86_Q35</span><br><span> </span><br><span> if SOUTHBRIDGE_INTEL_I82801IX</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23147">change 23147</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23147"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I67fdb3fd1557e68bb2ed2b135c0b3a6a13783605 </div>
<div style="display:none"> Gerrit-Change-Number: 23147 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>