[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Reduce storage size
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Thu Jan 4 12:26:14 CET 2018
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23088
Change subject: nb/intel/sandybridge: Reduce storage size
......................................................................
nb/intel/sandybridge: Reduce storage size
* Reduce storage size of raminit structure (and mrc cache).
* Get rid of function dram_dimm_mapping as everything can be calculated from
existing information.
* Add checks to make sure the unsigned raminit timings doesn't overflow.
Tested on Lenovo T430.
Change-Id: Ia3bb026fb1bd81b66f8a5be333760990d924071f
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/raminit_ivy.c
M src/northbridge/intel/sandybridge/raminit_sandy.c
5 files changed, 21 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/23088/1
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 12384b4..9f84010 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -68,7 +68,6 @@
memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0]));
ctrl->channel_size_mb[channel] = 0;
ctrl->cmd_stretch[channel] = 0;
- ctrl->mad_dimm[channel] = 0;
memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0]));
memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0]));
}
@@ -271,7 +270,7 @@
}
if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc)
&& dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) {
- const int ref_card_offset_table[6][6] = {
+ const u8 ref_card_offset_table[6][6] = {
{ 0, 0, 0, 0, 2, 2, },
{ 0, 0, 0, 0, 2, 2, },
{ 0, 0, 0, 0, 2, 2, },
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index eaef5f7..7f53c41 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -293,13 +293,13 @@
}
}
-void dram_dimm_mapping(ramctr_timing *ctrl)
+void dram_dimm_set_mapping(const ramctr_timing *ctrl)
{
int channel;
- dimm_info *info = &ctrl->info;
+ const dimm_info *info = &ctrl->info;
FOR_ALL_CHANNELS {
- dimm_attr *dimmA, *dimmB;
+ const dimm_attr *dimmA, *dimmB;
u32 reg = 0;
if (info->dimm[channel][0].size_mb >=
@@ -330,21 +330,13 @@
if ((dimmA && (dimmA->ranks > 0))
|| (dimmB && (dimmB->ranks > 0))) {
- ctrl->mad_dimm[channel] = reg;
+ MCHBAR32(0x5004 + channel * 4) = reg;
} else {
- ctrl->mad_dimm[channel] = 0;
+ MCHBAR32(0x5004 + channel * 4) = 0;
}
}
}
-void dram_dimm_set_mapping(ramctr_timing * ctrl)
-{
- int channel;
- FOR_ALL_CHANNELS {
- MCHBAR32(0x5004 + channel * 4) = ctrl->mad_dimm[channel];
- }
-}
-
void dram_zones(ramctr_timing * ctrl, int training)
{
u32 reg, ch0size, ch1size;
@@ -2109,8 +2101,9 @@
for (timC_delta = -5; timC_delta <= 5; timC_delta++) {
FOR_ALL_LANES {
+ const int timC = saved_rt.lanes[lane].timC + timC_delta;
ctrl->timings[channel][slotrank].lanes[lane].timC =
- saved_rt.lanes[lane].timC + timC_delta;
+ MIN(MAX(timC, 0), MAX_TIMC);
}
program_timings(ctrl, channel);
FOR_ALL_LANES {
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index ab6e592..ede0414 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -57,7 +57,7 @@
/* Register 4028. One nibble per slotrank. */
u8 val_4028;
- int val_320c;
+ int16_t val_320c;
struct ram_lane_timings {
/* lane register offset 0x10. */
@@ -66,7 +66,7 @@
u8 falling; /* bits 20 - 26. */
/* lane register offset 0x20. */
- int timC; /* bit 0 - 5, 19. */
+ u16 timC; /* bit 0 - 5, 19. */
u16 timB; /* bits 8 - 13, 15 - 17. */
} lanes[NUM_LANES];
};
@@ -111,21 +111,20 @@
u16 reg_5064b0; /* bits 0-11. */
u8 rankmap[NUM_CHANNELS];
- int ref_card_offset[NUM_CHANNELS];
- u32 mad_dimm[NUM_CHANNELS];
- int channel_size_mb[NUM_CHANNELS];
- u32 cmd_stretch[NUM_CHANNELS];
+ u8 ref_card_offset[NUM_CHANNELS];
+ u16 channel_size_mb[NUM_CHANNELS];
+ u8 cmd_stretch[NUM_CHANNELS];
- int reg_c14_offset;
- int reg_320c_range_threshold;
+ int16_t reg_c14_offset;
+ u8 reg_320c_range_threshold;
- int edge_offset[3];
- int timC_offset[3];
+ u8 edge_offset[3];
+ u8 timC_offset[3];
- int extended_temperature_range;
- int auto_self_refresh;
+ u8 extended_temperature_range;
+ u8 auto_self_refresh;
- int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS];
+ u8 rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS];
struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS];
@@ -157,8 +156,7 @@
void dram_find_common_params(ramctr_timing *ctrl);
void dram_xover(ramctr_timing * ctrl);
void dram_timing_regs(ramctr_timing * ctrl);
-void dram_dimm_mapping(ramctr_timing *ctrl);
-void dram_dimm_set_mapping(ramctr_timing * ctrl);
+void dram_dimm_set_mapping(const ramctr_timing *ctrl);
void dram_zones(ramctr_timing * ctrl, int training);
unsigned int get_mem_min_tck(void);
void dram_memorymap(ramctr_timing * ctrl, int me_uma_size);
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 675ac71..a94a825 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -642,8 +642,6 @@
if (!fast_boot) {
/* Find fastest common supported parameters */
dram_find_common_params(ctrl);
-
- dram_dimm_mapping(ctrl);
}
/* Set MCU frequency */
diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c
index 3acc563..289fb76 100644
--- a/src/northbridge/intel/sandybridge/raminit_sandy.c
+++ b/src/northbridge/intel/sandybridge/raminit_sandy.c
@@ -412,8 +412,6 @@
if (!fast_boot) {
/* Find fastest common supported parameters */
dram_find_common_params(ctrl);
-
- dram_dimm_mapping(ctrl);
}
/* Set MCU frequency */
--
To view, visit https://review.coreboot.org/23088
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia3bb026fb1bd81b66f8a5be333760990d924071f
Gerrit-Change-Number: 23088
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
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