<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23088">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/sandybridge: Reduce storage size<br><br>* Reduce storage size of raminit structure (and mrc cache).<br>* Get rid of function dram_dimm_mapping as everything can be calculated from<br> existing information.<br>* Add checks to make sure the unsigned raminit timings doesn't overflow.<br><br>Tested on Lenovo T430.<br><br>Change-Id: Ia3bb026fb1bd81b66f8a5be333760990d924071f<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/northbridge/intel/sandybridge/raminit.c<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>M src/northbridge/intel/sandybridge/raminit_common.h<br>M src/northbridge/intel/sandybridge/raminit_ivy.c<br>M src/northbridge/intel/sandybridge/raminit_sandy.c<br>5 files changed, 21 insertions(+), 35 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/23088/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c</span><br><span>index 12384b4..9f84010 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit.c</span><br><span>@@ -68,7 +68,6 @@</span><br><span> memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0]));</span><br><span> ctrl->channel_size_mb[channel] = 0;</span><br><span> ctrl->cmd_stretch[channel] = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->mad_dimm[channel] = 0;</span><br><span> memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0]));</span><br><span> memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0]));</span><br><span> }</span><br><span>@@ -271,7 +270,7 @@</span><br><span> }</span><br><span> if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc)</span><br><span> && dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) {</span><br><span style="color: hsl(0, 100%, 40%);">- const int ref_card_offset_table[6][6] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 ref_card_offset_table[6][6] = {</span><br><span> { 0, 0, 0, 0, 2, 2, },</span><br><span> { 0, 0, 0, 0, 2, 2, },</span><br><span> { 0, 0, 0, 0, 2, 2, },</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>index eaef5f7..7f53c41 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>@@ -293,13 +293,13 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void dram_dimm_mapping(ramctr_timing *ctrl)</span><br><span style="color: hsl(120, 100%, 40%);">+void dram_dimm_set_mapping(const ramctr_timing *ctrl)</span><br><span> {</span><br><span> int channel;</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_info *info = &ctrl->info;</span><br><span style="color: hsl(120, 100%, 40%);">+ const dimm_info *info = &ctrl->info;</span><br><span> </span><br><span> FOR_ALL_CHANNELS {</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_attr *dimmA, *dimmB;</span><br><span style="color: hsl(120, 100%, 40%);">+ const dimm_attr *dimmA, *dimmB;</span><br><span> u32 reg = 0;</span><br><span> </span><br><span> if (info->dimm[channel][0].size_mb >=</span><br><span>@@ -330,21 +330,13 @@</span><br><span> </span><br><span> if ((dimmA && (dimmA->ranks > 0))</span><br><span> || (dimmB && (dimmB->ranks > 0))) {</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->mad_dimm[channel] = reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5004 + channel * 4) = reg;</span><br><span> } else {</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->mad_dimm[channel] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5004 + channel * 4) = 0;</span><br><span> }</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void dram_dimm_set_mapping(ramctr_timing * ctrl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int channel;</span><br><span style="color: hsl(0, 100%, 40%);">- FOR_ALL_CHANNELS {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x5004 + channel * 4) = ctrl->mad_dimm[channel];</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void dram_zones(ramctr_timing * ctrl, int training)</span><br><span> {</span><br><span> u32 reg, ch0size, ch1size;</span><br><span>@@ -2109,8 +2101,9 @@</span><br><span> </span><br><span> for (timC_delta = -5; timC_delta <= 5; timC_delta++) {</span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(120, 100%, 40%);">+ const int timC = saved_rt.lanes[lane].timC + timC_delta;</span><br><span> ctrl->timings[channel][slotrank].lanes[lane].timC =</span><br><span style="color: hsl(0, 100%, 40%);">- saved_rt.lanes[lane].timC + timC_delta;</span><br><span style="color: hsl(120, 100%, 40%);">+ MIN(MAX(timC, 0), MAX_TIMC);</span><br><span> }</span><br><span> program_timings(ctrl, channel);</span><br><span> FOR_ALL_LANES {</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h</span><br><span>index ab6e592..ede0414 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_common.h</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_common.h</span><br><span>@@ -57,7 +57,7 @@</span><br><span> /* Register 4028. One nibble per slotrank. */</span><br><span> u8 val_4028;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- int val_320c;</span><br><span style="color: hsl(120, 100%, 40%);">+ int16_t val_320c;</span><br><span> </span><br><span> struct ram_lane_timings {</span><br><span> /* lane register offset 0x10. */</span><br><span>@@ -66,7 +66,7 @@</span><br><span> u8 falling; /* bits 20 - 26. */</span><br><span> </span><br><span> /* lane register offset 0x20. */</span><br><span style="color: hsl(0, 100%, 40%);">- int timC; /* bit 0 - 5, 19. */</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 timC; /* bit 0 - 5, 19. */</span><br><span> u16 timB; /* bits 8 - 13, 15 - 17. */</span><br><span> } lanes[NUM_LANES];</span><br><span> };</span><br><span>@@ -111,21 +111,20 @@</span><br><span> u16 reg_5064b0; /* bits 0-11. */</span><br><span> </span><br><span> u8 rankmap[NUM_CHANNELS];</span><br><span style="color: hsl(0, 100%, 40%);">- int ref_card_offset[NUM_CHANNELS];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 mad_dimm[NUM_CHANNELS];</span><br><span style="color: hsl(0, 100%, 40%);">- int channel_size_mb[NUM_CHANNELS];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 cmd_stretch[NUM_CHANNELS];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ref_card_offset[NUM_CHANNELS];</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 channel_size_mb[NUM_CHANNELS];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 cmd_stretch[NUM_CHANNELS];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- int reg_c14_offset;</span><br><span style="color: hsl(0, 100%, 40%);">- int reg_320c_range_threshold;</span><br><span style="color: hsl(120, 100%, 40%);">+ int16_t reg_c14_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reg_320c_range_threshold;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- int edge_offset[3];</span><br><span style="color: hsl(0, 100%, 40%);">- int timC_offset[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 edge_offset[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 timC_offset[3];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- int extended_temperature_range;</span><br><span style="color: hsl(0, 100%, 40%);">- int auto_self_refresh;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 extended_temperature_range;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 auto_self_refresh;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS];</span><br><span> </span><br><span> struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS];</span><br><span> </span><br><span>@@ -157,8 +156,7 @@</span><br><span> void dram_find_common_params(ramctr_timing *ctrl);</span><br><span> void dram_xover(ramctr_timing * ctrl);</span><br><span> void dram_timing_regs(ramctr_timing * ctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-void dram_dimm_mapping(ramctr_timing *ctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-void dram_dimm_set_mapping(ramctr_timing * ctrl);</span><br><span style="color: hsl(120, 100%, 40%);">+void dram_dimm_set_mapping(const ramctr_timing *ctrl);</span><br><span> void dram_zones(ramctr_timing * ctrl, int training);</span><br><span> unsigned int get_mem_min_tck(void);</span><br><span> void dram_memorymap(ramctr_timing * ctrl, int me_uma_size);</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c</span><br><span>index 675ac71..a94a825 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_ivy.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c</span><br><span>@@ -642,8 +642,6 @@</span><br><span> if (!fast_boot) {</span><br><span> /* Find fastest common supported parameters */</span><br><span> dram_find_common_params(ctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dram_dimm_mapping(ctrl);</span><br><span> }</span><br><span> </span><br><span> /* Set MCU frequency */</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c</span><br><span>index 3acc563..289fb76 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_sandy.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_sandy.c</span><br><span>@@ -412,8 +412,6 @@</span><br><span> if (!fast_boot) {</span><br><span> /* Find fastest common supported parameters */</span><br><span> dram_find_common_params(ctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dram_dimm_mapping(ctrl);</span><br><span> }</span><br><span> </span><br><span> /* Set MCU frequency */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23088">change 23088</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia3bb026fb1bd81b66f8a5be333760990d924071f </div>
<div style="display:none"> Gerrit-Change-Number: 23088 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>