[coreboot-gerrit] Change in coreboot[master]: mb/google/kahlee: Initialize WLAN GPIOs early.

[Justin TerAvest (Code Review)]

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/24916


Change subject: mb/google/kahlee: Initialize WLAN GPIOs early.
......................................................................

mb/google/kahlee: Initialize WLAN GPIOs early.

The GPIOs for PCIe reset and power enable for WLAN must be set up before
amdinitearly for wlan to function.

BUG=b:73898539
TEST=Boot, see WLAN controller in lspci

Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b
Signed-off-by: Justin TerAvest <teravest at chromium.org>
---
M src/mainboard/google/kahlee/bootblock/bootblock.c
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/kahlee/variants/kahlee/gpio.c
4 files changed, 34 insertions(+), 6 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/24916/1

diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 4a65d8f..e125c2c 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -20,6 +20,15 @@
 #include <variant/ec.h>
 #include <variant/gpio.h>
 
+
+void bootblock_mainboard_early_init(void)
+{
+	size_t num_gpios;
+	const struct soc_amd_stoneyridge_gpio *gpios;
+	gpios = variant_pre_init_gpio_table(&num_gpios);
+	sb_program_gpios(gpios, num_gpios);
+}
+
 void bootblock_mainboard_init(void)
 {
 	size_t num_gpios;
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index de70be4..e23c9cf 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -20,6 +20,17 @@
 #include <stdlib.h>
 
 /*
+ * Pins that must be set up before amdinitearly go here.
+ */
+const static struct soc_amd_stoneyridge_gpio gpio_set_stage_pre_init[] = {
+	/* GPIO_4 - EN_PP3300_WLAN */
+	PAD_GPO(GPIO_4, HIGH),
+
+	/* GPIO_70 - WLAN_PE_RST_L */
+	PAD_GPO(GPIO_70, HIGH),
+};
+
+/*
  * As a rule of thumb, GPIO pins used by coreboot should be initialized at
  * bootblock while GPIO pins used only by the OS should be initialized at
  * ramstage.
@@ -34,9 +45,6 @@
 	/* GPIO_3 - MEM_VOLT_SEL */
 	PAD_GPI(GPIO_3, PULL_UP),
 
-	/* GPIO_4 - EN_PP3300_WLAN */
-	PAD_GPO(GPIO_4, HIGH),
-
 	/* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */
 	PAD_GPI(GPIO_5, PULL_UP),
 
@@ -89,9 +97,6 @@
 	/* GPIO_42 - S5_MUX_CTRL */
 	PAD_NF(GPIO_42, S5_MUX_CTRL, PULL_NONE),
 
-	/* GPIO_70 - WLAN_PE_RST_L */
-	PAD_GPO(GPIO_70, HIGH),
-
 	/* GPIO_74 - LPC_CLK0_EC_R */
 	PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN),
 
@@ -255,6 +260,13 @@
 };
 
 const __attribute__((weak))
+struct soc_amd_stoneyridge_gpio *variant_pre_init_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(gpio_set_stage_pre_init);
+	return gpio_set_stage_pre_init;
+}
+
+const __attribute__((weak))
 struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size)
 {
 	*size = ARRAY_SIZE(gpio_set_stage_reset);
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
index 83ee119..188d35c 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
@@ -27,6 +27,7 @@
 int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len);
 int variant_get_xhci_oc_map(uint16_t *usb_oc_map);
 int variant_get_ehci_oc_map(uint16_t *usb_oc_map);
+const struct soc_amd_stoneyridge_gpio *variant_pre_init_gpio_table(size_t *size);
 const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size);
 const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size);
 
diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
index d1cc017..ec1888f 100644
--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c
+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
@@ -96,6 +96,12 @@
 	{GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H },
 };
 
+const struct soc_amd_stoneyridge_gpio *variant_pre_init_gpio_table(size_t *size)
+{
+	*size = 0;
+	return NULL;
+}
+
 const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size)
 {
 	*size = ARRAY_SIZE(gpio_set_stage_reset);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b
Gerrit-Change-Number: 24916
Gerrit-PatchSet: 1
Gerrit-Owner: Justin TerAvest <teravest at chromium.org>
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