[coreboot-gerrit] Change in coreboot[master]: [WIP]mb/google/octopus: Enable TPM on GSPI

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/24907


Change subject: [WIP]mb/google/octopus: Enable TPM on GSPI
......................................................................

[WIP]mb/google/octopus: Enable TPM on GSPI

BUG=b:73133848
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/octopus/variants/baseboard/devicetree.cb
M src/mainboard/google/octopus/variants/baseboard/gpio.c
3 files changed, 41 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/24907/1

diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 0f30316..f1c8d8f 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -63,4 +63,20 @@
 config INCLUDE_NHLT_BLOBS
 	bool "Include blobs for audio."
 
+config DRIVER_TPM_SPI_BUS
+	depends on OCTOPUS_USE_SPI_TPM
+	default 0x1
+
+# Select this option to enable use of cr50 SPI TPM on octopus.
+config OCTOPUS_USE_SPI_TPM
+	bool
+	default y
+	select MAINBOARD_HAS_SPI_TPM_CR50
+	select SPI_TPM
+	select TPM2
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 63 # GPE0_DW1_31 (GPIO_63)
+
 endif # BOARD_GOOGLE_OCTOPUS
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index 6248a88..5f34fd9 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -3,6 +3,13 @@
 		device lapic 0 on end
 	end
 
+	# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
+	# communication before memory is up.
+	register "gspi[0]" = "{
+		.speed_mhz = 1,
+		.early_init = 1,
+	}"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 on  end	# - DPTF
@@ -69,7 +76,14 @@
 		device pci 18.1 off end	# - UART 1
 		device pci 18.2 on  end	# - UART 2
 		device pci 18.3 off end	# - UART 3
-		device pci 19.0 on  end	# - SPI 0
+		device pci 19.0 on 
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63)"
+				device spi 0 on end
+			end
+		end # - GSPI 0
 		device pci 19.1 off end	# - SPI 1
 		device pci 19.2 on  end	# - SPI 2
 		device pci 1a.0 on  end	# - PWM
diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c
index 5bd2556..6c78782 100644
--- a/src/mainboard/google/octopus/variants/baseboard/gpio.c
+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c
@@ -266,6 +266,16 @@
 
 /* GPIOs needed prior to ramstage. */
 static const struct pad_config early_gpio_table[] = {
+#if IS_ENABLED(CONFIG_OCTOPUS_USE_SPI_TPM)
+/* GSPI0_CLK */         PAD_CFG_NF(GPIO_79, NONE, DEEP,
+				NF1), /* H1_SLAVE_SPI_CLK_R */
+/* GSPI0_CS# */         PAD_CFG_NF(GPIO_80, NONE, DEEP,
+				NF1), /* H1_SLAVE_SPI_CS_L_R */
+/* GSPI0_MISO */        PAD_CFG_NF(GPIO_81, NONE, DEEP,
+				NF1), /* H1_SLAVE_SPI_MISO */
+/* GSPI0_MOSI */        PAD_CFG_NF(GPIO_82, NONE, DEEP,
+				NF1), /* H1_SLAVE_SPI_MOSI_R */
+#endif
 };
 
 const struct pad_config *__attribute__((weak))

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf
Gerrit-Change-Number: 24907
Gerrit-PatchSet: 1
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
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