<p>Ravishankar Sarawadi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24907">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]mb/google/octopus: Enable TPM on GSPI<br><br>BUG=b:73133848<br>BRANCH=None<br>TEST=Build coreboot for Octopus board.<br><br>Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf<br>Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com><br>---<br>M src/mainboard/google/octopus/Kconfig<br>M src/mainboard/google/octopus/variants/baseboard/devicetree.cb<br>M src/mainboard/google/octopus/variants/baseboard/gpio.c<br>3 files changed, 41 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/24907/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig</span><br><span>index 0f30316..f1c8d8f 100644</span><br><span>--- a/src/mainboard/google/octopus/Kconfig</span><br><span>+++ b/src/mainboard/google/octopus/Kconfig</span><br><span>@@ -63,4 +63,20 @@</span><br><span> config INCLUDE_NHLT_BLOBS</span><br><span> bool "Include blobs for audio."</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DRIVER_TPM_SPI_BUS</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on OCTOPUS_USE_SPI_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Select this option to enable use of cr50 SPI TPM on octopus.</span><br><span style="color: hsl(120, 100%, 40%);">+config OCTOPUS_USE_SPI_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_SPI_TPM_CR50</span><br><span style="color: hsl(120, 100%, 40%);">+ select SPI_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ select TPM2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config TPM_TIS_ACPI_INTERRUPT</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 63 # GPE0_DW1_31 (GPIO_63)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif # BOARD_GOOGLE_OCTOPUS</span><br><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>index 6248a88..5f34fd9 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>@@ -3,6 +3,13 @@</span><br><span> device lapic 0 on end</span><br><span> end</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ # communication before memory is up.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gspi[0]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_mhz = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device domain 0 on</span><br><span> device pci 00.0 on end # - Host Bridge</span><br><span> device pci 00.1 on end # - DPTF</span><br><span>@@ -69,7 +76,14 @@</span><br><span> device pci 18.1 off end # - UART 1</span><br><span> device pci 18.2 on end # - UART 2</span><br><span> device pci 18.3 off end # - UART 3</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.0 on end # - SPI 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on </span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/spi/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device spi 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - GSPI 0</span><br><span> device pci 19.1 off end # - SPI 1</span><br><span> device pci 19.2 on end # - SPI 2</span><br><span> device pci 1a.0 on end # - PWM</span><br><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c</span><br><span>index 5bd2556..6c78782 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c</span><br><span>@@ -266,6 +266,16 @@</span><br><span> </span><br><span> /* GPIOs needed prior to ramstage. */</span><br><span> static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_OCTOPUS_USE_SPI_TPM)</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CLK */ PAD_CFG_NF(GPIO_79, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* H1_SLAVE_SPI_CLK_R */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NF(GPIO_80, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* H1_SLAVE_SPI_CS_L_R */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MISO */ PAD_CFG_NF(GPIO_81, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* H1_SLAVE_SPI_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_NF(GPIO_82, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* H1_SLAVE_SPI_MOSI_R */</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> };</span><br><span> </span><br><span> const struct pad_config *__attribute__((weak))</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24907">change 24907</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24907"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf </div>
<div style="display:none"> Gerrit-Change-Number: 24907 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>