[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/apollolake: Add support for GSPI
Ravishankar Sarawadi (Code Review)
gerrit at coreboot.org
Tue Feb 27 22:38:32 CET 2018
Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/24906
Change subject: [WIP]soc/intel/apollolake: Add support for GSPI
......................................................................
[WIP]soc/intel/apollolake: Add support for GSPI
BUG=b:73133848
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/chip.h
A src/soc/intel/apollolake/gspi.c
M src/soc/intel/apollolake/include/soc/iomap.h
5 files changed, 86 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/24906/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 9729773..585b8dd 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -9,6 +9,7 @@
select SOC_INTEL_APOLLOLAKE
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_SGX
+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
help
Intel GLK support
@@ -374,4 +375,8 @@
help
Use eSPI bus instead of LPC
+config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
+ int
+ default 3
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 68f2947..ab4da93 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -11,6 +11,7 @@
bootblock-y += bootblock/bootblock.c
bootblock-y += car.c
bootblock-y += heci.c
+bootblock-$(CONFIG_SOC_INTEL_GLK) += gspi.c
bootblock-y += i2c.c
bootblock-y += lpc.c
bootblock-y += mmap_boot.c
@@ -21,6 +22,7 @@
romstage-y += car.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
+romstage-$(CONFIG_SOC_INTEL_GLK) += gspi.c
romstage-y += heci.c
romstage-y += i2c.c
romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
@@ -48,6 +50,7 @@
ramstage-y += cse.c
ramstage-y += elog.c
ramstage-y += graphics.c
+ramstage-$(CONFIG_SOC_INTEL_GLK) += gspi.c
ramstage-y += heci.c
ramstage-y += i2c.c
ramstage-y += lpc.c
@@ -73,6 +76,7 @@
verstage-y += car.c
verstage-y += i2c.c
+verstage-$(CONFIG_SOC_INTEL_GLK) += gspi.c
verstage-y += heci.c
verstage-y += memmap.c
verstage-y += mmap_boot.c
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 8573cf4..681d244 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -20,6 +20,7 @@
#define _SOC_APOLLOLAKE_CHIP_H_
#include <commonlib/helpers.h>
+#include <intelblocks/gspi.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
#include <intelblocks/lpc_lib.h>
@@ -38,6 +39,9 @@
};
struct soc_intel_apollolake_config {
+ /* GSPI */
+ struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+
/*
* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
* four CLKREQ inputs, but six root ports. Root ports without an
diff --git a/src/soc/intel/apollolake/gspi.c b/src/soc/intel/apollolake/gspi.c
new file mode 100644
index 0000000..ca48aac
--- /dev/null
+++ b/src/soc/intel/apollolake/gspi.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <device/device.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/spi.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include "chip.h"
+
+const struct gspi_cfg *gspi_get_soc_cfg(void)
+{
+ DEVTREE_CONST struct soc_intel_apollolake_config *config;
+ int devfn = SA_DEVFN_ROOT;
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+ __func__);
+ return NULL;
+ }
+
+ config = dev->chip_info;
+
+ return &config->gspi[0];
+}
+
+uintptr_t gspi_get_soc_early_base(void)
+{
+ return EARLY_GSPI_BASE_ADDRESS;
+}
+
+/*
+ * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
+ * the bus # accordingly when referring to SPI / GSPI bus numbers.
+ */
+#define GSPI_TO_SPI_BUS(x) ((x) + 1)
+#define SPI_TO_GSPI_BUS(x) ((x) - 1)
+
+int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
+{
+ if (spi_bus == 0)
+ return -1;
+
+ *gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
+ if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
+ return -1;
+
+ return 0;
+}
+
+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
+{
+ if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
+ return -1;
+
+ return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
+}
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index d4cd095..7e6a795 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -48,6 +48,7 @@
/* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
#define PRERAM_SPI_BASE_ADDRESS 0xfe010000
+#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
/* Temporary BAR for early I2C bus access */
#define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x)))
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37
Gerrit-Change-Number: 24906
Gerrit-PatchSet: 1
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
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