<p>Ravishankar Sarawadi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24906">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]soc/intel/apollolake: Add support for GSPI<br><br>BUG=b:73133848<br>BRANCH=None<br>TEST=Build coreboot for Octopus board.<br><br>Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37<br>Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com><br>---<br>M src/soc/intel/apollolake/Kconfig<br>M src/soc/intel/apollolake/Makefile.inc<br>M src/soc/intel/apollolake/chip.h<br>A src/soc/intel/apollolake/gspi.c<br>M src/soc/intel/apollolake/include/soc/iomap.h<br>5 files changed, 86 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/24906/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig</span><br><span>index 9729773..585b8dd 100644</span><br><span>--- a/src/soc/intel/apollolake/Kconfig</span><br><span>+++ b/src/soc/intel/apollolake/Kconfig</span><br><span>@@ -9,6 +9,7 @@</span><br><span> select SOC_INTEL_APOLLOLAKE</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT</span><br><span> select SOC_INTEL_COMMON_BLOCK_SGX</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2</span><br><span> help</span><br><span> Intel GLK support</span><br><span> </span><br><span>@@ -374,4 +375,8 @@</span><br><span> help</span><br><span> Use eSPI bus instead of LPC</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_GSPI_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc</span><br><span>index 68f2947..ab4da93 100644</span><br><span>--- a/src/soc/intel/apollolake/Makefile.inc</span><br><span>+++ b/src/soc/intel/apollolake/Makefile.inc</span><br><span>@@ -11,6 +11,7 @@</span><br><span> bootblock-y += bootblock/bootblock.c</span><br><span> bootblock-y += car.c</span><br><span> bootblock-y += heci.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SOC_INTEL_GLK) += gspi.c</span><br><span> bootblock-y += i2c.c</span><br><span> bootblock-y += lpc.c</span><br><span> bootblock-y += mmap_boot.c</span><br><span>@@ -21,6 +22,7 @@</span><br><span> </span><br><span> romstage-y += car.c</span><br><span> romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SOC_INTEL_GLK) += gspi.c</span><br><span> romstage-y += heci.c</span><br><span> romstage-y += i2c.c</span><br><span> romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c</span><br><span>@@ -48,6 +50,7 @@</span><br><span> ramstage-y += cse.c</span><br><span> ramstage-y += elog.c</span><br><span> ramstage-y += graphics.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SOC_INTEL_GLK) += gspi.c</span><br><span> ramstage-y += heci.c</span><br><span> ramstage-y += i2c.c</span><br><span> ramstage-y += lpc.c</span><br><span>@@ -73,6 +76,7 @@</span><br><span> </span><br><span> verstage-y += car.c</span><br><span> verstage-y += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_SOC_INTEL_GLK) += gspi.c</span><br><span> verstage-y += heci.c</span><br><span> verstage-y += memmap.c</span><br><span> verstage-y += mmap_boot.c</span><br><span>diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h</span><br><span>index 8573cf4..681d244 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.h</span><br><span>+++ b/src/soc/intel/apollolake/chip.h</span><br><span>@@ -20,6 +20,7 @@</span><br><span> #define _SOC_APOLLOLAKE_CHIP_H_</span><br><span> </span><br><span> #include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span> #include <soc/gpe.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <intelblocks/lpc_lib.h></span><br><span>@@ -38,6 +39,9 @@</span><br><span> };</span><br><span> </span><br><span> struct soc_intel_apollolake_config {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has</span><br><span> * four CLKREQ inputs, but six root ports. Root ports without an</span><br><span>diff --git a/src/soc/intel/apollolake/gspi.c b/src/soc/intel/apollolake/gspi.c</span><br><span>new file mode 100644</span><br><span>index 0000000..ca48aac</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/apollolake/gspi.c</span><br><span>@@ -0,0 +1,72 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct gspi_cfg *gspi_get_soc_cfg(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct soc_intel_apollolake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ int devfn = SA_DEVFN_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return &config->gspi[0];</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t gspi_get_soc_early_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return EARLY_GSPI_BASE_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust</span><br><span style="color: hsl(120, 100%, 40%);">+ * the bus # accordingly when referring to SPI / GSPI bus numbers.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GSPI_TO_SPI_BUS(x) ((x) + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_TO_GSPI_BUS(x) ((x) - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (spi_bus == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *gspi_bus = SPI_TO_GSPI_BUS(spi_bus);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h</span><br><span>index d4cd095..7e6a795 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/iomap.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/iomap.h</span><br><span>@@ -48,6 +48,7 @@</span><br><span> </span><br><span> /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */</span><br><span> #define PRERAM_SPI_BASE_ADDRESS 0xfe010000</span><br><span style="color: hsl(120, 100%, 40%);">+#define EARLY_GSPI_BASE_ADDRESS 0xfe011000</span><br><span> </span><br><span> /* Temporary BAR for early I2C bus access */</span><br><span> #define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x)))</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24906">change 24906</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24906"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 </div>
<div style="display:none"> Gerrit-Change-Number: 24906 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>