[coreboot-gerrit] Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
Philipp Deppenwiese (Code Review)
gerrit at coreboot.org
Tue Feb 27 22:27:31 CET 2018
Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/24905
Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot.
......................................................................
drivers/tpm: Add TPM ramstage driver for devices without vboot.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin at das-labor.org>
---
M src/cpu/intel/haswell/romstage.c
M src/drivers/intel/fsp1_1/romstage.c
A src/drivers/tpm/Kconfig
A src/drivers/tpm/Makefile.inc
A src/drivers/tpm/tpm.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/google/stout/romstage.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/lenovo/x201/romstage.c
M src/mainboard/pcengines/apu2/romstage.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/northbridge/intel/sandybridge/romstage.c
M src/security/tpm/Makefile.inc
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/broadwell/romstage/romstage.c
19 files changed, 48 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/24905/1
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 1c293d4..2cfc19c 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -42,7 +42,6 @@
#include "northbridge/intel/haswell/raminit.h"
#include "southbridge/intel/lynxpoint/pch.h"
#include "southbridge/intel/lynxpoint/me.h"
-#include <security/tpm/tspi.h>
static inline void reset_system(void)
{
@@ -245,8 +244,6 @@
romstage_handoff_init(wake_from_s3);
post_code(0x3f);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(wake_from_s3);
}
asmlinkage void romstage_after_car(void)
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index f542038..8515219 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -36,7 +36,6 @@
#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
-#include <security/tpm/tspi.h>
#include <vendorcode/google/chromeos/chromeos.h>
asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
@@ -166,16 +165,6 @@
if (romstage_handoff_init(
params->power_state->prev_sleep_state == ACPI_S3) < 0)
hard_reset();
-
- /*
- * Initialize the TPM, unless the TPM was already initialized
- * in verstage and used to verify romstage.
- */
- if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) &&
- !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&
- !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
- tpm_setup(params->power_state->prev_sleep_state ==
- ACPI_S3);
}
void after_cache_as_ram_stage(void)
diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig
new file mode 100644
index 0000000..da8434b
--- /dev/null
+++ b/src/drivers/tpm/Kconfig
@@ -0,0 +1,4 @@
+config TPM_INIT
+ bool
+ default y if TPM1 || TPM2
+ depends on !VBOOT
diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc
new file mode 100644
index 0000000..4e80600
--- /dev/null
+++ b/src/drivers/tpm/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_TPM_INIT) += tpm.c
diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c
new file mode 100644
index 0000000..3799f2a
--- /dev/null
+++ b/src/drivers/tpm/tpm.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Facebook Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <stddef.h>
+#include <option.h>
+#include <bootstate.h>
+#include <device/device.h>
+#include <security/tpm/tspi.h>
+
+#if IS_ENABLED(CONFIG_ARCH_X86)
+#include <arch/acpi.h>
+#endif
+
+static void init_tpm_dev(void *unused)
+{
+#if IS_ENABLED(CONFIG_ARCH_X86)
+ int s3resume = acpi_is_wakeup_s3();
+ tpm_setup(s3resume);
+#else
+ tpm_setup(false);
+#endif
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, init_tpm_dev, NULL);
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 8bcb062..aecf3b2 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -46,7 +46,6 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include <security/tpm/tspi.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -626,9 +625,6 @@
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707);
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
}
/**
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 9cf2cc8..bf05be9 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -35,7 +35,6 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#include <cbfs.h>
#include <southbridge/intel/bd82x6x/chip.h>
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 9e68493..f44da4e 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -35,7 +35,6 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include <cbfs.h>
-#include <security/tpm/tspi.h>
#include "ec/compal/ene932/ec.h"
void pch_enable_lpc(void)
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 387ed76..ffebe53 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -35,7 +35,6 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include <bootmode.h>
-#include <security/tpm/tspi.h>
#include <cbfs.h>
#include <ec/quanta/it8518/ec.h>
#include "ec.h"
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 9ecfeec..5efe62d 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -35,7 +35,6 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#define SIO_PORT 0x164e
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 951b40b..986226e7 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -35,7 +35,6 @@
#include <timestamp.h>
#include <arch/acpi.h>
#include <cbmem.h>
-#include <security/tpm/tspi.h>
#include "dock.h"
#include "arch/early_variables.h"
@@ -285,7 +284,4 @@
acpi_prepare_for_resume();
else
quick_ram_check();
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 093cad6..af48e30 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -33,7 +33,6 @@
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <Fch/Fch.h>
-#include <security/tpm/tspi.h>
#include "gpio_ftns.h"
@@ -103,9 +102,6 @@
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(false);
-
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
}
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index c066ca4..d2231aa 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -28,7 +28,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <bootmode.h>
-#include <security/tpm/tspi.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 2572d77..2cc7e50 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -37,7 +37,6 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
#include <superio/smsc/lpc47n207/lpc47n207.h>
#endif
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index c334a51..eefbfa2 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -28,7 +28,6 @@
#include <device/pci_def.h>
#include <device/device.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#include <northbridge/intel/sandybridge/chip.h>
#include "southbridge/intel/bd82x6x/pch.h"
#include <southbridge/intel/common/gpio.h>
@@ -116,8 +115,5 @@
northbridge_romstage_finalize(s3resume);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
-
post_code(0x3f);
}
diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc
index 74cd978..fb8edf28 100644
--- a/src/security/tpm/Makefile.inc
+++ b/src/security/tpm/Makefile.inc
@@ -3,16 +3,16 @@
ifeq ($(CONFIG_TPM1),y)
ramstage-y += tss/tcg-1.2/tss.c
-romstage-y += tss/tcg-1.2/tss.c
+romstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c
verstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c
postcar-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c
## TSPI
ramstage-y += tspi/tspi.c
-romstage-y += tspi/tspi.c
+romstage-$(CONFIG_VBOOT) += tspi/tspi.c
verstage-$(CONFIG_VBOOT) += tspi/tspi.c
postcar-$(CONFIG_VBOOT) += tspi/tspi.c
@@ -23,8 +23,8 @@
ramstage-y += tss/tcg-2.0/tss_marshaling.c
ramstage-y += tss/tcg-2.0/tss.c
-romstage-y += tss/tcg-2.0/tss_marshaling.c
-romstage-y += tss/tcg-2.0/tss.c
+romstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c
+romstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c
verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c
verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c
@@ -35,8 +35,8 @@
## TSPI
ramstage-y += tspi/tspi.c
-romstage-y += tspi/tspi.c
+romstage-$(CONFIG_VBOOT) += tspi/tspi.c
verstage-$(CONFIG_VBOOT) += tspi/tspi.c
postcar-$(CONFIG_VBOOT) += tspi/tspi.c
@@ -45,8 +45,8 @@
ifeq ($(CONFIG_TPM_CR50),y)
ramstage-y += tss/vendor/cr50/tss.c
-romstage-y += tss/vendor/cr50/tss.c
+romstage-$(CONFIG_VBOOT) += tss/vendor/cr50/tss.c
verstage-$(CONFIG_VBOOT) += tss/vendor/cr50/tss.c
postcar-$(CONFIG_VBOOT) += tss/vendor/cr50/tss.c
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index e911724..765fc09 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -30,7 +30,6 @@
#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
-#include <security/tpm/tspi.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
@@ -228,9 +227,6 @@
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(prev_sleep_state == ACPI_S3);
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(prev_sleep_state == ACPI_S3);
}
void asmlinkage romstage_after_car(void)
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 2fbe406..f485dfd 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -43,7 +43,6 @@
#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/spi.h>
-#include <security/tpm/tspi.h>
void program_base_addresses(void)
{
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index f66824f..8762f9f 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -25,7 +25,6 @@
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
#include <elog.h>
-#include <security/tpm/tspi.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <stage_cache.h>
@@ -109,9 +108,6 @@
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(params->power_state->prev_sleep_state == ACPI_S3);
}
asmlinkage void romstage_after_car(void)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Gerrit-Change-Number: 24905
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
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