<p>Philipp Deppenwiese has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24905">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">drivers/tpm: Add TPM ramstage driver for devices without vboot.<br><br>Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e<br>Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org><br>---<br>M src/cpu/intel/haswell/romstage.c<br>M src/drivers/intel/fsp1_1/romstage.c<br>A src/drivers/tpm/Kconfig<br>A src/drivers/tpm/Makefile.inc<br>A src/drivers/tpm/tpm.c<br>M src/mainboard/asus/kgpe-d16/romstage.c<br>M src/mainboard/google/link/romstage.c<br>M src/mainboard/google/parrot/romstage.c<br>M src/mainboard/google/stout/romstage.c<br>M src/mainboard/intel/emeraldlake2/romstage.c<br>M src/mainboard/lenovo/x201/romstage.c<br>M src/mainboard/pcengines/apu2/romstage.c<br>M src/mainboard/samsung/lumpy/romstage.c<br>M src/mainboard/samsung/stumpy/romstage.c<br>M src/northbridge/intel/sandybridge/romstage.c<br>M src/security/tpm/Makefile.inc<br>M src/soc/intel/baytrail/romstage/romstage.c<br>M src/soc/intel/braswell/romstage/romstage.c<br>M src/soc/intel/broadwell/romstage/romstage.c<br>19 files changed, 48 insertions(+), 51 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/24905/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c</span><br><span>index 1c293d4..2cfc19c 100644</span><br><span>--- a/src/cpu/intel/haswell/romstage.c</span><br><span>+++ b/src/cpu/intel/haswell/romstage.c</span><br><span>@@ -42,7 +42,6 @@</span><br><span> #include "northbridge/intel/haswell/raminit.h"</span><br><span> #include "southbridge/intel/lynxpoint/pch.h"</span><br><span> #include "southbridge/intel/lynxpoint/me.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> </span><br><span> static inline void reset_system(void)</span><br><span> {</span><br><span>@@ -245,8 +244,6 @@</span><br><span> romstage_handoff_init(wake_from_s3);</span><br><span> </span><br><span> post_code(0x3f);</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))</span><br><span style="color: hsl(0, 100%, 40%);">- tpm_setup(wake_from_s3);</span><br><span> }</span><br><span> </span><br><span> asmlinkage void romstage_after_car(void)</span><br><span>diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c</span><br><span>index f542038..8515219 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/romstage.c</span><br><span>+++ b/src/drivers/intel/fsp1_1/romstage.c</span><br><span>@@ -36,7 +36,6 @@</span><br><span> #include <stage_cache.h></span><br><span> #include <string.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> </span><br><span> asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)</span><br><span>@@ -166,16 +165,6 @@</span><br><span> if (romstage_handoff_init(</span><br><span> params->power_state->prev_sleep_state == ACPI_S3) < 0)</span><br><span> hard_reset();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Initialize the TPM, unless the TPM was already initialized</span><br><span style="color: hsl(0, 100%, 40%);">- * in verstage and used to verify romstage.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) &&</span><br><span style="color: hsl(0, 100%, 40%);">- !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&</span><br><span style="color: hsl(0, 100%, 40%);">- !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))</span><br><span style="color: hsl(0, 100%, 40%);">- tpm_setup(params->power_state->prev_sleep_state ==</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_S3);</span><br><span> }</span><br><span> </span><br><span> void after_cache_as_ram_stage(void)</span><br><span>diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..da8434b</span><br><span>--- /dev/null</span><br><span>+++ b/src/drivers/tpm/Kconfig</span><br><span>@@ -0,0 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config TPM_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y if TPM1 || TPM2</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on !VBOOT</span><br><span>diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..4e80600</span><br><span>--- /dev/null</span><br><span>+++ b/src/drivers/tpm/Makefile.inc</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_TPM_INIT) += tpm.c</span><br><span>diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c</span><br><span>new file mode 100644</span><br><span>index 0000000..3799f2a</span><br><span>--- /dev/null</span><br><span>+++ b/src/drivers/tpm/tpm.c</span><br><span>@@ -0,0 +1,37 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Facebook Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stddef.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <option.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootstate.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/tpm/tspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_ARCH_X86)</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void init_tpm_dev(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_ARCH_X86)</span><br><span style="color: hsl(120, 100%, 40%);">+ int s3resume = acpi_is_wakeup_s3();</span><br><span style="color: hsl(120, 100%, 40%);">+ tpm_setup(s3resume);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ tpm_setup(false);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, init_tpm_dev, NULL);</span><br><span>diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c</span><br><span>index 8bcb062..aecf3b2 100644</span><br><span>--- a/src/mainboard/asus/kgpe-d16/romstage.c</span><br><span>+++ b/src/mainboard/asus/kgpe-d16/romstage.c</span><br><span>@@ -46,7 +46,6 @@</span><br><span> #include <cpu/amd/family_10h-family_15h/init_cpus.h></span><br><span> #include <arch/early_variables.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> </span><br><span> #include "resourcemap.c"</span><br><span> #include "cpu/amd/quadcore/quadcore.c"</span><br><span>@@ -626,9 +625,6 @@</span><br><span> pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707);</span><br><span> pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);</span><br><span> pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))</span><br><span style="color: hsl(0, 100%, 40%);">- tpm_setup(s3resume);</span><br><span> }</span><br><span> </span><br><span> /**</span><br><span>diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c</span><br><span>index 9cf2cc8..bf05be9 100644</span><br><span>--- a/src/mainboard/google/link/romstage.c</span><br><span>+++ b/src/mainboard/google/link/romstage.c</span><br><span>@@ -35,7 +35,6 @@</span><br><span> #include <arch/cpu.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> #include <cbfs.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/chip.h></span><br><span>diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c</span><br><span>index 9e68493..f44da4e 100644</span><br><span>--- a/src/mainboard/google/parrot/romstage.c</span><br><span>+++ b/src/mainboard/google/parrot/romstage.c</span><br><span>@@ -35,7 +35,6 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <halt.h></span><br><span> #include <cbfs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> #include "ec/compal/ene932/ec.h"</span><br><span> </span><br><span> void pch_enable_lpc(void)</span><br><span>diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c</span><br><span>index 387ed76..ffebe53 100644</span><br><span>--- a/src/mainboard/google/stout/romstage.c</span><br><span>+++ b/src/mainboard/google/stout/romstage.c</span><br><span>@@ -35,7 +35,6 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <halt.h></span><br><span> #include <bootmode.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> #include <cbfs.h></span><br><span> #include <ec/quanta/it8518/ec.h></span><br><span> #include "ec.h"</span><br><span>diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>index 9ecfeec..5efe62d 100644</span><br><span>--- a/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>+++ b/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>@@ -35,7 +35,6 @@</span><br><span> #include <arch/cpu.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> </span><br><span> #define SIO_PORT 0x164e</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c</span><br><span>index 951b40b..986226e7 100644</span><br><span>--- a/src/mainboard/lenovo/x201/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x201/romstage.c</span><br><span>@@ -35,7 +35,6 @@</span><br><span> #include <timestamp.h></span><br><span> #include <arch/acpi.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> </span><br><span> #include "dock.h"</span><br><span> #include "arch/early_variables.h"</span><br><span>@@ -285,7 +284,4 @@</span><br><span> acpi_prepare_for_resume();</span><br><span> else</span><br><span> quick_ram_check();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))</span><br><span style="color: hsl(0, 100%, 40%);">- tpm_setup(s3resume);</span><br><span> }</span><br><span>diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c</span><br><span>index 093cad6..af48e30 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/romstage.c</span><br><span>+++ b/src/mainboard/pcengines/apu2/romstage.c</span><br><span>@@ -33,7 +33,6 @@</span><br><span> #include <cpu/x86/lapic.h></span><br><span> #include <southbridge/amd/pi/hudson/hudson.h></span><br><span> #include <Fch/Fch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> </span><br><span> #include "gpio_ftns.h"</span><br><span> </span><br><span>@@ -103,9 +102,6 @@</span><br><span> post_code(0x41);</span><br><span> AGESAWRAPPER(amdinitenv);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))</span><br><span style="color: hsl(0, 100%, 40%);">- tpm_setup(false);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> outb(0xEA, 0xCD6);</span><br><span> outb(0x1, 0xcd7);</span><br><span> }</span><br><span>diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c</span><br><span>index c066ca4..d2231aa 100644</span><br><span>--- a/src/mainboard/samsung/lumpy/romstage.c</span><br><span>+++ b/src/mainboard/samsung/lumpy/romstage.c</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #include <cbmem.h></span><br><span> #include <console/console.h></span><br><span> #include <bootmode.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span>diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c</span><br><span>index 2572d77..2cc7e50 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/romstage.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/romstage.c</span><br><span>@@ -37,7 +37,6 @@</span><br><span> #include <arch/cpu.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)</span><br><span> #include <superio/smsc/lpc47n207/lpc47n207.h></span><br><span> #endif</span><br><span>diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c</span><br><span>index c334a51..eefbfa2 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/romstage.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/romstage.c</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include <device/device.h></span><br><span> #include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> #include <northbridge/intel/sandybridge/chip.h></span><br><span> #include "southbridge/intel/bd82x6x/pch.h"</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span>@@ -116,8 +115,5 @@</span><br><span> </span><br><span> northbridge_romstage_finalize(s3resume);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))</span><br><span style="color: hsl(0, 100%, 40%);">- tpm_setup(s3resume);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> post_code(0x3f);</span><br><span> }</span><br><span>diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc</span><br><span>index 74cd978..fb8edf28 100644</span><br><span>--- a/src/security/tpm/Makefile.inc</span><br><span>+++ b/src/security/tpm/Makefile.inc</span><br><span>@@ -3,16 +3,16 @@</span><br><span> ifeq ($(CONFIG_TPM1),y)</span><br><span> </span><br><span> ramstage-y += tss/tcg-1.2/tss.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += tss/tcg-1.2/tss.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c</span><br><span> verstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c</span><br><span> postcar-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c</span><br><span> </span><br><span> ## TSPI</span><br><span> </span><br><span> ramstage-y += tspi/tspi.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += tspi/tspi.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_VBOOT) += tspi/tspi.c</span><br><span> verstage-$(CONFIG_VBOOT) += tspi/tspi.c</span><br><span> postcar-$(CONFIG_VBOOT) += tspi/tspi.c</span><br><span> </span><br><span>@@ -23,8 +23,8 @@</span><br><span> ramstage-y += tss/tcg-2.0/tss_marshaling.c</span><br><span> ramstage-y += tss/tcg-2.0/tss.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += tss/tcg-2.0/tss_marshaling.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += tss/tcg-2.0/tss.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c</span><br><span> </span><br><span> verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c</span><br><span> verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c</span><br><span>@@ -35,8 +35,8 @@</span><br><span> ## TSPI</span><br><span> </span><br><span> ramstage-y += tspi/tspi.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += tspi/tspi.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_VBOOT) += tspi/tspi.c</span><br><span> verstage-$(CONFIG_VBOOT) += tspi/tspi.c</span><br><span> postcar-$(CONFIG_VBOOT) += tspi/tspi.c</span><br><span> </span><br><span>@@ -45,8 +45,8 @@</span><br><span> ifeq ($(CONFIG_TPM_CR50),y)</span><br><span> </span><br><span> ramstage-y += tss/vendor/cr50/tss.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += tss/vendor/cr50/tss.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_VBOOT) += tss/vendor/cr50/tss.c</span><br><span> verstage-$(CONFIG_VBOOT) += tss/vendor/cr50/tss.c</span><br><span> postcar-$(CONFIG_VBOOT) += tss/vendor/cr50/tss.c</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>index e911724..765fc09 100644</span><br><span>--- a/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>@@ -30,7 +30,6 @@</span><br><span> #include <stage_cache.h></span><br><span> #include <string.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <soc/iomap.h></span><br><span>@@ -228,9 +227,6 @@</span><br><span> timestamp_add_now(TS_AFTER_INITRAM);</span><br><span> </span><br><span> romstage_handoff_init(prev_sleep_state == ACPI_S3);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))</span><br><span style="color: hsl(0, 100%, 40%);">- tpm_setup(prev_sleep_state == ACPI_S3);</span><br><span> }</span><br><span> </span><br><span> void asmlinkage romstage_after_car(void)</span><br><span>diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c</span><br><span>index 2fbe406..f485dfd 100644</span><br><span>--- a/src/soc/intel/braswell/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/braswell/romstage/romstage.c</span><br><span>@@ -43,7 +43,6 @@</span><br><span> #include <soc/romstage.h></span><br><span> #include <soc/smm.h></span><br><span> #include <soc/spi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> </span><br><span> void program_base_addresses(void)</span><br><span> {</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>index f66824f..8762f9f 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>@@ -25,7 +25,6 @@</span><br><span> #include <cbmem.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <elog.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/tpm/tspi.h></span><br><span> #include <program_loading.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <stage_cache.h></span><br><span>@@ -109,9 +108,6 @@</span><br><span> timestamp_add_now(TS_AFTER_INITRAM);</span><br><span> </span><br><span> romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))</span><br><span style="color: hsl(0, 100%, 40%);">- tpm_setup(params->power_state->prev_sleep_state == ACPI_S3);</span><br><span> }</span><br><span> </span><br><span> asmlinkage void romstage_after_car(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24905">change 24905</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e </div>
<div style="display:none"> Gerrit-Change-Number: 24905 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>