[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Move PCR DMI programming into bootblock

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23866


Change subject: soc/intel/skylake: Move PCR DMI programming into bootblock
......................................................................

soc/intel/skylake: Move PCR DMI programming into bootblock

As per PCH BWG 2.5.16, setup LPC IO Enables PCR[DMI] + 2774h bit
[15:0] to the same value program in LPC PCI  offset 82h. Hence
moving the required programming from lpc.c to pch.c.

Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/lpc.c
2 files changed, 28 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/23866/1

diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 34cfaa3..e80758d 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -36,6 +36,8 @@
 #include <soc/pmc.h>
 #include <soc/smbus.h>
 
+#define PCR_DMI_DMICTL		0x2234
+#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
@@ -158,14 +160,38 @@
 	outw(tcocnt, tcobase + TCO1_CNT);
 }
 
+static int pch_check_decode_enable(uint16_t lpc_en)
+{
+	uint32_t dmi_control;
+
+	/*
+	 * This cycle decoding is only allowed to set when
+	 * DMICTL.SRLOCK is 0
+	 */
+	dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+	if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
+		return -1;
+	return 0;
+}
+
 void pch_early_iorange_init(void)
 {
+	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+			LPC_IOE_EC_62_66;
+
 	/* IO Decode Range */
 	lpc_io_setup_comm_a_b();
 
 	/* IO Decode Enable */
-	lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
-		LPC_IOE_EC_62_66);
+	if (pch_check_decode_enable(io_enables) == 0) {
+		lpc_enable_fixed_io_ranges(io_enables);
+		/*
+		 * As per PCH BWG 2.5.16.
+		 * Setup LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
+		 * value program in LPC PCI  offset 82h
+		 */
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+	}
 
 	/* Program generic IO Decode Range */
 	pch_enable_lpc();
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index d0678c9..3d1dd7b 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -82,17 +82,11 @@
 
 void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
 {
-	uint16_t lpc_en;
-
 	/* Mirror these same settings in DMI PCR */
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-
-	/* LPC IO Decode Enable */
-	lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
-	pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en);
 }
 
 static const struct reg_script pch_misc_init_script[] = {

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8
Gerrit-Change-Number: 23866
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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