<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23866">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Move PCR DMI programming into bootblock<br><br>As per PCH BWG 2.5.16, setup LPC IO Enables PCR[DMI] + 2774h bit<br>[15:0] to the same value program in LPC PCI offset 82h. Hence<br>moving the required programming from lpc.c to pch.c.<br><br>Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/bootblock/pch.c<br>M src/soc/intel/skylake/lpc.c<br>2 files changed, 28 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/23866/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c</span><br><span>index 34cfaa3..e80758d 100644</span><br><span>--- a/src/soc/intel/skylake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/skylake/bootblock/pch.c</span><br><span>@@ -36,6 +36,8 @@</span><br><span> #include <soc/pmc.h></span><br><span> #include <soc/smbus.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_DMICTL 0x2234</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_DMICTL_SRLOCK (1 << 31)</span><br><span> #define PCR_DMI_ACPIBA 0x27B4</span><br><span> #define PCR_DMI_ACPIBDID 0x27B8</span><br><span> #define PCR_DMI_PMBASEA 0x27AC</span><br><span>@@ -158,14 +160,38 @@</span><br><span> outw(tcocnt, tcobase + TCO1_CNT);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static int pch_check_decode_enable(uint16_t lpc_en)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dmi_control;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This cycle decoding is only allowed to set when</span><br><span style="color: hsl(120, 100%, 40%);">+ * DMICTL.SRLOCK is 0</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dmi_control & PCR_DMI_DMICTL_SRLOCK)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void pch_early_iorange_init(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |</span><br><span style="color: hsl(120, 100%, 40%);">+ LPC_IOE_EC_62_66;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* IO Decode Range */</span><br><span> lpc_io_setup_comm_a_b();</span><br><span> </span><br><span> /* IO Decode Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |</span><br><span style="color: hsl(0, 100%, 40%);">- LPC_IOE_EC_62_66);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_check_decode_enable(io_enables) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_enable_fixed_io_ranges(io_enables);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * As per PCH BWG 2.5.16.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Setup LPC IO Enables PCR[DMI] + 2774h [15:0] to the same</span><br><span style="color: hsl(120, 100%, 40%);">+ * value program in LPC PCI offset 82h</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> /* Program generic IO Decode Range */</span><br><span> pch_enable_lpc();</span><br><span>diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c</span><br><span>index d0678c9..3d1dd7b 100644</span><br><span>--- a/src/soc/intel/skylake/lpc.c</span><br><span>+++ b/src/soc/intel/skylake/lpc.c</span><br><span>@@ -82,17 +82,11 @@</span><br><span> </span><br><span> void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t lpc_en;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Mirror these same settings in DMI PCR */</span><br><span> pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);</span><br><span> pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);</span><br><span> pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);</span><br><span> pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* LPC IO Decode Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en);</span><br><span> }</span><br><span> </span><br><span> static const struct reg_script pch_misc_init_script[] = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23866">change 23866</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8 </div>
<div style="display:none"> Gerrit-Change-Number: 23866 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>