[coreboot-gerrit] Change in coreboot[master]: Revert "UPSTREAM: soc/intel/cannonlake: Add support for C state and P...
Nick Vaccaro (Code Review)
gerrit at coreboot.org
Wed Feb 21 23:20:14 CET 2018
Hello Nick Vaccaro,
I'd like you to do a code review. Please visit
https://review.coreboot.org/23838
to review the following change.
Change subject: Revert "UPSTREAM: soc/intel/cannonlake: Add support for C state and P state"
......................................................................
Revert "UPSTREAM: soc/intel/cannonlake: Add support for C state and P state"
C states causes problems with emmc on meowth, so reverting C states
for now.
This reverts commit 6ff1410d371a75eda45f4f19610d644e397eccc4.
BUG=b:71586766
BRANCH=master
TEST=none
Change-Id: Icde3a177020aab303a61b40d138ea03f204895b4
Signed-off-by: Nick Vaccaro <nvaccaro at chromium.org>
---
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/include/soc/cpu.h
3 files changed, 1 insertion(+), 136 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/23838/1
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 9dcaa33..4e2a027 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -33,143 +33,9 @@
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <string.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
-/*
- * List of supported C-states in this processor.
- */
-enum {
- C_STATE_C0, /* 0 */
- C_STATE_C1, /* 1 */
- C_STATE_C1E, /* 2 */
- C_STATE_C6_SHORT_LAT, /* 3 */
- C_STATE_C6_LONG_LAT, /* 4 */
- C_STATE_C7_SHORT_LAT, /* 5 */
- C_STATE_C7_LONG_LAT, /* 6 */
- C_STATE_C7S_SHORT_LAT, /* 7 */
- C_STATE_C7S_LONG_LAT, /* 8 */
- C_STATE_C8, /* 9 */
- C_STATE_C9, /* 10 */
- C_STATE_C10, /* 11 */
- NUM_C_STATES
-};
-
-#define MWAIT_RES(state, sub_state) \
- { \
- .addrl = (((state) << 4) | (sub_state)), \
- .space_id = ACPI_ADDRESS_SPACE_FIXED, \
- .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
- .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
- .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
- }
-
-static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
- [C_STATE_C0] = {},
- [C_STATE_C1] = {
- .latency = 0,
- .power = C1_POWER,
- .resource = MWAIT_RES(0, 0),
- },
- [C_STATE_C1E] = {
- .latency = 0,
- .power = C1_POWER,
- .resource = MWAIT_RES(0, 1),
- },
- [C_STATE_C6_SHORT_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = C6_POWER,
- .resource = MWAIT_RES(2, 0),
- },
- [C_STATE_C6_LONG_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = C6_POWER,
- .resource = MWAIT_RES(2, 1),
- },
- [C_STATE_C7_SHORT_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = C7_POWER,
- .resource = MWAIT_RES(3, 0),
- },
- [C_STATE_C7_LONG_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = C7_POWER,
- .resource = MWAIT_RES(3, 1),
- },
- [C_STATE_C7S_SHORT_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = C7_POWER,
- .resource = MWAIT_RES(3, 2),
- },
- [C_STATE_C7S_LONG_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = C7_POWER,
- .resource = MWAIT_RES(3, 3),
- },
- [C_STATE_C8] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = C8_POWER,
- .resource = MWAIT_RES(4, 0),
- },
- [C_STATE_C9] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = C9_POWER,
- .resource = MWAIT_RES(5, 0),
- },
- [C_STATE_C10] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = C10_POWER,
- .resource = MWAIT_RES(6, 0),
- },
-};
-
-static int cstate_set_s0ix[] = {
- C_STATE_C1E,
- C_STATE_C6_LONG_LAT,
- C_STATE_C7S_LONG_LAT
-};
-
-static int cstate_set_non_s0ix[] = {
- C_STATE_C1E,
- C_STATE_C7S_LONG_LAT,
- C_STATE_C10
-};
-
-acpi_cstate_t *soc_get_cstate_map(size_t *entries)
-{
- static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
- ARRAY_SIZE(cstate_set_non_s0ix))];
- int *set;
- int i;
- device_t dev = SA_DEV_ROOT;
- config_t *config = dev->chip_info;
- int is_s0ix_enable = config->s0ix_enable;
-
- if (is_s0ix_enable) {
- *entries = ARRAY_SIZE(cstate_set_s0ix);
- set = cstate_set_s0ix;
- } else {
- *entries = ARRAY_SIZE(cstate_set_non_s0ix);
- set = cstate_set_non_s0ix;
- }
-
- for (i = 0; i < *entries; i++) {
- memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
- map[i].ctype = i + 1;
- }
- return map;
-}
-
-void soc_power_states_generation(int core_id, int cores_per_package)
-{
- device_t dev = SA_DEV_ROOT;
- config_t *config = dev->chip_info;
- if (config->eist_enable)
- /* Generate P-state tables */
- generate_p_state_entries(core_id, cores_per_package);
-}
-
void soc_fill_fadt(acpi_fadt_t *fadt)
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 68f95d3..604ec47 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -157,7 +157,6 @@
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.init = DEVICE_NOOP,
- .acpi_fill_ssdt_generator = generate_cpu_entries,
};
static void soc_enable(device_t dev)
diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h
index dfc7183..a7379e9 100644
--- a/src/soc/intel/cannonlake/include/soc/cpu.h
+++ b/src/soc/intel/cannonlake/include/soc/cpu.h
@@ -19,7 +19,6 @@
#include <arch/cpu.h>
#include <device/device.h>
-#include <intelblocks/msr.h>
/* Latency times in units of 32768ns */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d
@@ -31,6 +30,7 @@
/* Power in units of mW */
#define C1_POWER 0x3e8
+#define C3_POWER 0x1f4
#define C6_POWER 0x15e
#define C7_POWER 0xc8
#define C8_POWER 0xc8
--
To view, visit https://review.coreboot.org/23838
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icde3a177020aab303a61b40d138ea03f204895b4
Gerrit-Change-Number: 23838
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro at chromium.org>
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