<p>Nick Vaccaro would like Nick Vaccaro to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/23838">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Revert "UPSTREAM: soc/intel/cannonlake: Add support for C state and P state"<br><br>C states causes problems with emmc on meowth, so reverting C states<br>for now.<br><br>This reverts commit 6ff1410d371a75eda45f4f19610d644e397eccc4.<br><br>BUG=b:71586766<br>BRANCH=master<br>TEST=none<br><br>Change-Id: Icde3a177020aab303a61b40d138ea03f204895b4<br>Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org><br>---<br>M src/soc/intel/cannonlake/acpi.c<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/include/soc/cpu.h<br>3 files changed, 1 insertion(+), 136 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/23838/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c</span><br><span>index 9dcaa33..4e2a027 100644</span><br><span>--- a/src/soc/intel/cannonlake/acpi.c</span><br><span>+++ b/src/soc/intel/cannonlake/acpi.c</span><br><span>@@ -33,143 +33,9 @@</span><br><span> #include <soc/nvs.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span> #include <vendorcode/google/chromeos/gnvs.h></span><br><span> #include <wrdd.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * List of supported C-states in this processor.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C0, /* 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C1, /* 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C1E, /* 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C6_SHORT_LAT, /* 3 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C6_LONG_LAT, /* 4 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C7_SHORT_LAT, /* 5 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C7_LONG_LAT, /* 6 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C7S_SHORT_LAT, /* 7 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C7S_LONG_LAT, /* 8 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C8, /* 9 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C9, /* 10 */</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C10, /* 11 */</span><br><span style="color: hsl(0, 100%, 40%);">- NUM_C_STATES</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MWAIT_RES(state, sub_state) \</span><br><span style="color: hsl(0, 100%, 40%);">- { \</span><br><span style="color: hsl(0, 100%, 40%);">- .addrl = (((state) << 4) | (sub_state)), \</span><br><span style="color: hsl(0, 100%, 40%);">- .space_id = ACPI_ADDRESS_SPACE_FIXED, \</span><br><span style="color: hsl(0, 100%, 40%);">- .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \</span><br><span style="color: hsl(0, 100%, 40%);">- .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \</span><br><span style="color: hsl(0, 100%, 40%);">- .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const acpi_cstate_t cstate_map[NUM_C_STATES] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C0] = {},</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C1] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C1_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(0, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C1E] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C1_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(0, 1),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C6_SHORT_LAT] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C6_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(2, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C6_LONG_LAT] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C6_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(2, 1),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C7_SHORT_LAT] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C7_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(3, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C7_LONG_LAT] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C7_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(3, 1),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C7S_SHORT_LAT] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C7_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(3, 2),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C7S_LONG_LAT] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C7_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(3, 3),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C8] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C8_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(4, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C9] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C9_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(5, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- [C_STATE_C10] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),</span><br><span style="color: hsl(0, 100%, 40%);">- .power = C10_POWER,</span><br><span style="color: hsl(0, 100%, 40%);">- .resource = MWAIT_RES(6, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int cstate_set_s0ix[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C1E,</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C6_LONG_LAT,</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C7S_LONG_LAT</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int cstate_set_non_s0ix[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C1E,</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C7S_LONG_LAT,</span><br><span style="color: hsl(0, 100%, 40%);">- C_STATE_C10</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-acpi_cstate_t *soc_get_cstate_map(size_t *entries)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),</span><br><span style="color: hsl(0, 100%, 40%);">- ARRAY_SIZE(cstate_set_non_s0ix))];</span><br><span style="color: hsl(0, 100%, 40%);">- int *set;</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(0, 100%, 40%);">- config_t *config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">- int is_s0ix_enable = config->s0ix_enable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (is_s0ix_enable) {</span><br><span style="color: hsl(0, 100%, 40%);">- *entries = ARRAY_SIZE(cstate_set_s0ix);</span><br><span style="color: hsl(0, 100%, 40%);">- set = cstate_set_s0ix;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- *entries = ARRAY_SIZE(cstate_set_non_s0ix);</span><br><span style="color: hsl(0, 100%, 40%);">- set = cstate_set_non_s0ix;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < *entries; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));</span><br><span style="color: hsl(0, 100%, 40%);">- map[i].ctype = i + 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return map;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void soc_power_states_generation(int core_id, int cores_per_package)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(0, 100%, 40%);">- config_t *config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->eist_enable)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Generate P-state tables */</span><br><span style="color: hsl(0, 100%, 40%);">- generate_p_state_entries(core_id, cores_per_package);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void soc_fill_fadt(acpi_fadt_t *fadt)</span><br><span> {</span><br><span> const uint16_t pmbase = ACPI_BASE_ADDRESS;</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 68f95d3..604ec47 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -157,7 +157,6 @@</span><br><span> .set_resources = DEVICE_NOOP,</span><br><span> .enable_resources = DEVICE_NOOP,</span><br><span> .init = DEVICE_NOOP,</span><br><span style="color: hsl(0, 100%, 40%);">- .acpi_fill_ssdt_generator = generate_cpu_entries,</span><br><span> };</span><br><span> </span><br><span> static void soc_enable(device_t dev)</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h</span><br><span>index dfc7183..a7379e9 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/cpu.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/cpu.h</span><br><span>@@ -19,7 +19,6 @@</span><br><span> </span><br><span> #include <arch/cpu.h></span><br><span> #include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/msr.h></span><br><span> </span><br><span> /* Latency times in units of 32768ns */</span><br><span> #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d</span><br><span>@@ -31,6 +30,7 @@</span><br><span> </span><br><span> /* Power in units of mW */</span><br><span> #define C1_POWER 0x3e8</span><br><span style="color: hsl(120, 100%, 40%);">+#define C3_POWER 0x1f4</span><br><span> #define C6_POWER 0x15e</span><br><span> #define C7_POWER 0xc8</span><br><span> #define C8_POWER 0xc8</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23838">change 23838</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icde3a177020aab303a61b40d138ea03f204895b4 </div>
<div style="display:none"> Gerrit-Change-Number: 23838 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Nick Vaccaro <nvaccaro@chromium.org> </div>